Globalfoundries Singapore Pte. Ltd.

Xiaobo Qiu

Zhihong Luo

Benjamin Shui Chor Lau

Yi Liang

Yeung On Au

Swee Chen Hoo

Swee Chuen Hoo

A digital controlled oscillator (DCO) is provided that includes a plurality of selectable delay cells, a first load adjustment delay (LAD) cell, a second LAD cell, a first set of the load cells (LCs), a second set of the LCs and first and second capacitance elements. A number of the selectable delay cells that are part of a delay cell chain is configurable based on a delay cell number control vector. The delay cell chain generates a delay cell output signal that is received by the first LAD cell. The first set of the LCs generate a first load signal to control an amount of loading on the second LAD cell, and the second set of the LCs generate a second load signal to control loading on the first LAD cell. Substrate voltages of the first and second capacitance elements can be adjusted to adjust loading in the DCO.

Digitally controlled oscillator (DCO) for a phase locked loop (PLL) system

A PLL control system is provided that implements a phase tracer module to reduce lock time and output clock jitter. A second clock signal is generated by dividing a frequency of a reference clock signal. A feedback clock signal is generated based on a high-frequency clock signal from a digitally controlled oscillator (DCO) and a PLL feedback divide number. Lead/lag determination circuitry generates a lead/lag detection result that indicates whether the feedback clock signal leads or lags the second clock signal. A skew digitizer digitizes a skew between a falling edge of the second clock signal and a rising edge of the feedback clock signal to generate a skew signal. The phase tracer module processes the lead/lag detection result and the skew signal to generate a digital control signal that controls cycle time of the DCO to change frequency of the high-frequency clock signal.

Digital phase locked loop (PLL) system and method with phase tracing

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Singapore, Singapore

Xiaobo Qiu