International Business Machines Corporation

Qualcomm Incorporated

Globalfoundries Inc.

Cadence Design Systems, Inc.

Xiaobin Yuan

Mangal Prasad

Marshall Dale Tiner

Hung H Tran

Alan J Drake

Pawel Owczarczyk

Joseph Natonio

Michael Stephen Floyd

Pier Andrea Francese

David T Hui

Reinaldo Ariel Vega

Xiangdong Chen

Emre Alptekin

Gregory Scott Still

Todd Morgan Rasmus

Jae-Eun Park

Deleep R Nair

Weipeng Li

Jie Deng

Francesco A Campisano

Daniel K Tekleab

Nam Sung Kim

Mouna Safi-Harab

Pradeep Thiagarajan

Carrie Ellen Cox

Anirban Banerjee

Siqi Fan

Aida Varzaghani

Victor Git-Han Moy

Dimitrios Loizos

Hiu Ming Lam

Irina Gavshina

Varun Joshi

Jacob Lee Dahle

Kevin Robert Bartholomew

Dimitri Loizos

In some examples, a circuit can include a first buffer circuit that can be configured to receive a first clock signal and a first output voltage. The first buffer circuit can be configured to operate in a first voltage domain based on the first output voltage. The circuit can include a second buffer circuit configured to receive a second clock signal, the second buffer circuit being configured to operate in a second voltage domain based on the second output voltage. The first voltage domain can be different from the second voltage domain. In some examples, one of the first and second buffer circuits can be configured to provide one of the first and second clock signals as a clock output signal at a clock output terminal in response to a clock enable signal.

Systems and methods for communicating clock signals

A high-speed multiplexor comprises a set of differential input pairs to receive and mix a set of differential input signals at a differential output node pair. The high-speed multiplexer further comprises an active inductive load pair driven by the input stage using the mixed set of differential input signals. Each active inductive load comprises a p-channel field effect transistor (pFET) device connected to one of the differential output node pairs and a resistor connected between a gate node and a drain node of the pFET device. The multiplexer further comprises a first cross-coupling capacitor connected between the gate node of a first inductive load and a second output node of the differential output node pair and a second cross-coupling capacitor connected between the gate node of a second inductive load and a first output node of the differential output node pair.

High-speed multiplexer

An Electro-Static Discharge (ESD) protection circuit is disclosed. In some implementations, the ESD protection circuit includes a first ESD diode, a second ESD diode, a passive equalization network and a programmable resistor network. The first ESD diode is coupled to the passive equalization network. The programmable resistor network is coupled between the passive equalization network and the second ESD diode. The programmable resistor network can be programmed to place the ESD protection circuit in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.

T-coil enhanced ESD protection with passive equalization

The present embodiments relate generally to data communications, and more particularly to systems including high-speed serializer-deserializer circuits having TCOILs. One or more embodiments are directed to a four-terminal TCOIL structure that consumes the same amount of area on a chip as a traditional three-terminal structure, while providing more bandwidth and less reflection and group delay variation.

Compact four-terminal TCOIL

A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.

Fine delay structure with programmable delay ranges

Various clock frequency dividers are disclosed. Each frequency divider includes cascaded flip-flops and a feedback logic gate. First data inputs of the flip-flops are for propagating logic values along the cascaded flip-flops and the feedback gate for generating valid states of a sequence in response to a clock signal. Each frequency divider includes an invalid state elimination circuit configured to detect an invalid state at the outputs of the flip-flops and change it into a valid state in response to the clock signal. In some implementations, the invalid state elimination circuit includes a NOR gate to detect an all-zero invalid state and generate a control signal to cause the flip-flops to output logic values associated with a valid state or to cause a multiplexer to introduce a logic value associated with a valid state. In other implementations, the invalid state elimination circuit instead includes an AND gate to detect an all-ones invalid state.

Apparatus and method for clock signal frequency division using self-resetting, low power, linear feedback shift register (LFSR)

A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.

Apparatus and method for centrally controlling common mode voltages for a set of receivers

A tunnel field effect transistor (TFET) including a first doped source region for a first type TFET or a second doped source region for a second type TFET; a second doped drain region for the first type TFET or a first doped drain region for the second type TFET; a body region that is either intrinsic or doped, with a doping concentration less than that of the first or second source region, separating the first or second source from the first or second drain regions; a self-aligned etch cavity separating the first or second doped source and drain regions; a thin epitaxial channel region that is grown within the self-aligned etch cavity, covering at least the first or the second source region; a replacement gate stack comprising a high-k gate dielectric and one or a combination of metals and polysilicon; and sidewall spacers adjacent to the replacement gate stack.

Tunnel transistors with abrupt junctions

An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Multi-core dynamic frequency control system

A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.

Method of fabricating tunnel transistors with abrupt junctions

Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.

Peaking inductor array for peaking control unit of transceiver

One aspect of the present disclosure relates to a method for operating an amplifier, the amplifier including a variable resistor coupled between a source of a first input transistor and a source of a second input transistors, and a variable capacitor coupled between the source of the first input transistor and the source of the second input transistor. The method includes adjusting a resistance of the variable resistor to adjust a low-frequency gain of the amplifier, and adjusting a capacitance of the variable capacitor in an opposite direction as the adjustment to the resistance of the variable resistor.

Variable gain amplifier with coupled degeneration resistance and capacitance

In one implementation, an amplifier comprises a load circuit comprising a plurality of inductor cells, and a drive circuit configured to receive an input signal, and to drive the load circuit based on the input signal to generate an amplified signal. The amplifier also comprises a controller configured to tune a peaking gain of the amplifier by adjusting a number of the inductor cells that are enabled.

Amplifier with boosted peaking

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Carmel, NY, United States of America

Xiaobin Yuan