Altera Corporation

Xilinx, Inc.

Xiaobao Wang

Chiakang Sung

Khai Nguyen

Bonnie I Wang

Joseph Huang

In Whan Kim

Yan Chong

Tzung-Chin Chang

Philip Pan

Wayne Yeung

Gopinath Rangan

Gopi Rangan

Richard G Cliff

Phillip Pan

Arvind R Bomdica

Thomas Henry White

John Henry Bui

Gubo Huang

Sing-Keng Tan

Jonathan Chung

Andrew Tabalujan

Surgey Y Shumarayev

Myron Wai Wong

Sanjay K Charagulla

Balakrishna Jayadev

Sabarathnam Ekambaram

Amitava Majumdar

Henry Kim

Dirk Alan Reese

Shuxian Wu

Richard William Swanson

Pradeep Nagarajan

Hari Bilash Dubey

Jeffrey Tyhach

Zahir Parpia

Vss Prasad Babu Akurathi

Vipul Dutt Badoni

David S Smith

Sasi Rama S Lanka

Vinit Shah

Siva Charan Nimmagadda

Xuemei Xi

Im Whan Kim

Khai Huang

Burton M Leary

A memory controller includes driver circuitry, which includes main driver circuitry and hold driver circuitry. The main driver circuitry and hold driver circuitry are connected to an output node. The main driver circuitry comprises driver slice circuitries and outputs a first output signal to the output node based on a first input signal and a second input signal and a number of activated driver slice circuitries. The hold drive circuitry receive the first input signal and outputs a second output signal. The second output signal is delayed with reference to the first output signal by a first delay amount.

Boosted driver circuitry of a low voltage supply memory controller

Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.

Calibrated linear duty cycle correction

Examples herein relate to devices that include a strobe tree circuit for capturing data using a memory-sourced strobe. In an example, a device includes a data capture path including first and second flip-flops, and a strobe tree including a comparator and first and second multiplexers. The comparator is configured to output complementary signals on first and second output nodes. First and second selection input nodes of the first multiplexer are connected to the first and second output nodes of the comparator, respectively. First and second selection input nodes of the second multiplexer are connected to the second and first output nodes of the comparator, respectively. The read strobe tree is configured to provide first and second signals output from the first and second multiplexers to first and second nodes, respectively. Clock input nodes of the first and second flip-flops are connected to the first and second nodes, respectively.

Strobe tree circuit for capturing data using a memory-sourced strobe

Examples herein describe techniques for testing a receiver interface on a die. In one embodiment, the die includes tester circuitry which includes a digital to analog convertor (DAC) which outputs an analog test signal to a selector circuit (e.g., a multiplexer) which forwards the analog test signal to a receiver. By varying the analog test signal, the tester circuitry can identify one or more trip points corresponding to the receiver. That is, by monitoring the output of the receiver, a testing application can determine when the output of the receiver switches states thereby indicating that the analog test signal at the input of the receiver corresponds to the trip point of the receiver. In this manner, internal circuitry (e.g., the tester circuitry) can be used to test a receiver interface that may otherwise be inaccessible.

Testing an integrated circuit receiver in a package using a varying analog voltage

A die-to-die interconnect structure includes an interconnect network including a plurality of metal interconnect layers. The interconnect network is configured to electrically couple a first die and a second die mounted on a top surface of the die-to-die interconnect structure. A first metal interconnect layer of the plurality of metal interconnect layers includes a plurality of ground lines and a plurality of signal lines distributed across the first metal interconnect layer according to a GSSG pattern. In some examples, adjacent signal lines within the first metal interconnect layer are separated by a dielectric region. In some embodiments, a second metal interconnect layer of the plurality of metal interconnect layers is disposed above the first metal interconnect layer and includes a plurality of configurable signal/ground lines. By way of example, each of the plurality of configurable signal/ground lines is disposed over the dielectric region and within the second metal interconnect layer.

Systems providing interposer structures

Examples of the present disclosure provide example devices that include an integrated circuit that has debugging capability. In some examples, a device includes an integrated circuit die. The integrated circuit die includes an input/output (IO) base cell and a debug port. The IO base cell has an interface node and a feedback node. The interface node is configured to be coupled to memory, such as via an interposer, for communication therebetween. The IO base cell is configurable to selectively output to the feedback node a signal that is on the interface node. The debug port has an input node and an output node. The input node is electrically connected to the feedback node. The debug port is configurable to selectively output to the output node a signal that is on the input node. The output node is configured to be coupled to a pin exterior to the integrated circuit die.

Electronic device including integrated circuit with debug capabilities

Methods and apparatus relate to a 1-to-2 memory interface deserializer circuit that, in a training mode, independently positions even and odd strobes in respective even and odd data windows. In an illustrative example, the deserializer circuit may receive a data signal that encodes even and odd data streams on the rising (even) and falling (odd) edges of a strobe clock signal. During a training mode, the deserializer circuit may independently determine, for example, an optimal temporal delay for each of the even strobe and the odd strobe. Adjustable delay lines dedicated to each of the even and odd strobe signals may simultaneously detect valid data window edges to permit determination of a desired delay to optimally position the strobe signals. Various embodiments may advantageously reduce jitter associated with asymmetric strobe and/or data signals to achieve a predetermined specification (e.g., timing margins) within the corresponding data windows.

Training and tracking of DDR memory interface strobe timing

Examples herein describe a die that includes a testing system (e.g., testing circuitry) for measuring the actual resistance of on-die resistors. When testing the die, an I/O element (e.g., a solder bump) can be used to sweep a voltage across the on-die resistor. The testing system identifies when the voltage across the on-die resistor reaches a predefined reference voltage and measures the corresponding current. Using the measured current and the reference voltage, the testing system can identify the actual resistance of the on-die resistor. In one embodiment, the on-die resistor is tunable such if the on-die resistor has a divergent value, the die can adjust its resistance value to the desired value.

On-die resistor measurement

A transmitter includes: a driver circuit having a pull-up circuit, and a pull-down circuit, coupled to an output pad; a digitally controlled impedance (DCI) calibration circuit having a first reference driver, a second reference driver, and a reference resistor, the DCI calibration circuit configured to: generate a value for a first code by calibrating a first impedance in the first reference driver against the reference resistor; generate a value for a second code by calibrating a second impedance in the second reference driver against the first impedance; and adjust the value of the first code to match the first impedance with the second impedance; and a pre-driver circuit configured to supply the first code and the second code to the driver circuit for adjusting output impedance of the pull-up circuit and the pull-down circuit.

Digitally controlled impedance calibration for a driver using an on-die reference resistor

A pull-up leg of disclosed circuitry includes a pull-up pre-driver and a pull-up driver coupled to the pull-up pre-driver. A pull-down leg includes a pull-down pre-driver and a pull-down driver coupled to the pull-down pre-driver. An input/output pad is coupled between the pull-up driver and pull-down driver. A driver-and-termination control circuit is coupled to receive a tristate control signal, a termination control signal, and an input data signal. The driver-and-termination control circuit selects a drive mode, tristate mode, or termination mode in response to the tristate control signal and the termination control signal. The driver-and-termination control circuit drives a first data signal to the pull-up driver and drives a second data signal to the pull-down driver. The first and second data signals have equal logic states in the drive mode and have opposite logic states in the tristate and termination modes.

Integrated driver and termination circuit

A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.

On-die input reference voltage with self-calibrating duty cycle correction

An apparatus includes a plurality of adjustable driver circuits having output nodes coupled to a signal line. Each adjustable driver circuit is configured to drive the signal line with a portion of a total drive strength indicated by a value of a binary control signal. The apparatus also includes a delay circuit configured to delay the binary control signal provided to each adjustable driver circuit by a respective time period unique to the adjustable driver circuit.

Strength-adjustable driver

An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described.

Circuits for and methods of testing the operation of an input/output port

An integrated circuit may include a memory controller that interfaces with memory via one or more ports. A given port may be coupled to a comparator that receives data signals from the memory and a reference voltage signal and produces a corresponding output signal that identifies whether the data signals are logic one signals or logic zero signals. The memory controller may include detection circuitry coupled to the port that produces a target reference voltage signal for calibration of the reference voltage signal. The memory controller may include circuitry that produces the reference voltage signal based on control signals received from control circuitry. The control circuitry may generate the control signals to calibrate the reference voltage signal based on the target reference voltage.

Systems and methods for memory controller reference voltage calibration

A programmable receiver implemented in an integrated circuit device is described. The programmable receiver comprises a pre-amplifier circuit coupled to receive an input signal, the pre-amplifier circuit having a programmable current source; and an amplifier circuit coupled to receive an output of the pre-amplifier circuit; wherein the programmable current source is coupled to receive a control signal to enable the receiver to be switched between a high performance mode and a low performance mode. A method of implementing a programmable receiver in an integrated circuit is also described.

Programmable receivers implemented in an integrated circuit device

Growing community of inventors

Cupertino, CA, United States of America

Xiaobao Wang