Motorola Corporation

Freescale Semiconductor,inc.

Nxp Usa, Inc.

Nxp B.v.

Xiao Sun

Carmie A Hull

Yuan Li

Jayanta Bhadra

Joseph Gergen

Xiushan Feng

Wen Chen

Rohit Kumar Kaul

John C Chan

Eric Simard

Chi Duong

Xiaotao Chen

Jayanta Bahadra

An adaptive prefetcher for a shared system cache of a processing system including multiple requestors having a cache miss monitor and a prefetch controller. The cache miss monitor monitors requests for information from memory and identifies one of the requestors for which an identified cache line is requested. The prefetch controller submits an adaptive request for a subsequent cache line. The subsequent cache line may be determined based on a latency comparison between a loop latency (LL) of the prefetch controller and a stream latency (SL) of the identified requestor. A latency memory may be included that stores stream latencies for the requestors. The latency comparison may be used to determine how many cache lines to skip relative to the identified cache line, such as according to SL*SK<LL≤SL*(SK+1) in which SK is the number of cache lines to skip.

Adaptive prefetcher for shared system cache

Channel availability information associated with data traffic between a Master and a Slave within an interconnection network ('ICN') in a System-on-Chip ('SoC') is monitored by a channel performance monitor in order to improve the performance of the ICN. The channel availability information is fed back to certain Masters to control their data traffic into the ICN. The channel performance monitor monitors and evaluates the data traffic handled by switches within the ICN that can potentially interfere with communication paths between particular Masters and Slaves, and control the initiation of data traffic from predetermined Masters.

Performance monitor for interconnection network in an integrated circuit

A method, system, program control code, and hardware circuit are provided for predicting performance of an system-on-chip (SoC) () having a processor () and a master device () having shared access to a single-port memory () by activating a timer () in a Performance Monitoring Unit (PMU) () to measure a specified number of cycles of the processor in a defined measure instance and by activating a memory access counter () in the PMU to measure a first count of memory access requests to the single-port memory by the processor in the defined measure instance and to measure a second count of memory access requests to the single-port memory by the master device in the defined measure instance, so that the first and second counts are stored in memory.

Hardware, software and algorithm to precisely predict performance of SoC when a processor and other masters access single-port memory simultaneously

A method, system, and architecture () for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server () which receives specified hardware metric data () monitored at an integrated circuit device () in the field, identifies prioritized built-in self-test (BIST) fault detection tests () based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests () to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information () identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.

System architecture method and apparatus for adaptive hardware fault detection with hardware metrics subsystem

A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

Integrated circuit design verification through forced clock glitches

A method and apparatus to generate test sequences for pipeline hazards in a pipelined data processing system is presented. An executable specification for the architecture is compiled that includes macroarchitecture and microarchitecture information corresponding to each of the instructions supported by the architecture. A table ( ) is constructed from the executable specification that specifies the particular resource utilization parameters associated with each of the instruction types included in the instruction set supported. From this table a resource utilization parameter list ( ) is compiled that indicates the relative times at which resources are needed by each instruction and when these resources are released by the instruction. Comparisons between different entries in the resource utilization parameter list corresponding to the same resource are performed such that potential hazards are detected. A hazard list ( ) is then compiled that includes all of the hazards detected through the comparison operations utilizing the resource utilization parameter list ( ). This hazard list ( ) can then be used generate and qualify test sequences and to determine if hardware or software is overcompensating or undercompensating for the potential hazard conditions.

Method and apparatus for generation of pipeline hazard test sequences

A method and apparatus for identifying and detecting hazards is presented. An executable specification for the architecture is compiled that includes macroarchitecture and microarchitecture information corresponding to each of the instructions supported by the architecture. A table ( ) is constructed from the executable specification that specifies the particular resource utilization parameters associated with each of the instruction types included in the instruction set supported. From this table a resource utilization parameter list ( ) is compiled that indicates the relative times at which resources are needed by each instruction and when these resources are released by the instruction. Comparisons between different entries in the resource utilization parameter list corresponding to the same resource are performed such that potential hazards are detected. A hazard list ( ) is then compiled that includes all of the hazards detected through the comparison operations utilizing the resource utilization parameter list ( ).

Method and apparatus for pipeline hazard detection

Unique Input/Output Sequence (UIO) Sets are constructed to test conformance of a Machine (,) against a Finite State Machine (FSM) model (,). Unique Input/Output Sequence (UIO) Sets (,) uniquely identify FSM model states and may be Forward Unique I/O Sequences (FUIO), Backward Unique I/O Sequences (BUIO), Forward Unique I/O Sequence Sets (FUIOset), and/or Backward Unique I/O Sequence Sets (BUIOset). FSM model (,) state transitions are selected as Edges-Under-Test (EUT). A Set of EUT UIO Sets is identified comprising UIO Sets that uniquely identify either the source or destination FSM model (,) state of an EUT. One member is selected from the Set of EUT UIO Sets for a particular EUT, and each member of this UIO Set is concatenated with the EUT to form Test Subsequences (TS). These Test Subsequences are used to verify that the corresponding FSM transitions are successfully traversed by a Machine Under Test (MUT).

Method and apparatus for testing finite state machine (FSM) conformance utilizing unique input/output sequence (UIO) sets

A set of Unique Input/Output Sequence (UIO) Sets is identified for Finite State Machine (FSM) model (33) states. Each member of the Sets of UIO Sets is a UIO Set (63) which are sets of Input/Output (I/O) Sequences that each uniquely identifies FSM (33) states. FSM (33) state transitions are Edges-Under-Test (EUT). A Test Subsequence is constructed for each member of each UIO Set (63) selected for each EUT that includes the UIO Set member and the corresponding EUT. A Test Subsequence (TS) Graph (65) is constructed from the Test Subsequences by connecting Test Subsequence starting and ending states. A Verification Test Sequence for testing a Machine Under Test (14) for conformance with a FSM model (33) is constructed by touring the TS Graph (65).

Method and apparatus for constructing test subsequence graphs utilizing

Verification Test Sequences (43) (VTS) are constructed for use in testing conformance of a Machine-Under-Test (14) (MUT) with a Finite State Machine (33) (FSM) model. The number of incoming and outgoing Test Subsequence (TS) graph (39) micro-edges are determined for each TS graph (39) vertex or Finite State Machine (33) state. An Augmented Graph (95) is created (40) by constructing Test Subsequence (TS) micro-edge bridging sequences between TS graph vertices with relatively more incoming micro-edges and vertices with relatively more outgoing micro-edges. The newly symmetric Augmented Graph (95) is Euler Toured (42), generating Verification Test Sequences (43), used to test a Machine-Under-Test (14) for conformance with the FSM model (33).

Method and apparatus for constructing verification test sequences by

A Distinctness Measurement (DM) is determined (16) for Finite State Machine (FSM) state transitions. The DM is used to identify Unique Input/Output Sequence (UIO) Sets (63) that uniquely identify FSM (33) states. UIO Set members are combined with FSM transitions to form Test Subsequences (TS). Test Subsequences are connected (64) into Hierarchical TS Graphs (65), which are merged (38). The merged TS Graph (39) is augmented (94) and Euler Toured (28) to generate Verification Test Sequences (VTS). A VTS (43) tests conformance of a Machine-Under-Test (14) against a FSM (33) model.

Hierarchical Test Subsequence (TS) subgraphs and Finite State Machine (FSM) subgraphs are merged. Hierarchical FSM subgraphs are merged (82) by connecting FSM model (33) child subgraph transitions or graph edges with states or vertices in the FSM parent subgraph. Matching is done based on Input/Output sequences. This merging (82) is repeated until all FSM child subgraphs are merged into FSM childless subgraphs. FSM childless subgraphs are Merged FSM graphs (83). Hierarchical Test Subsequence (TS) subgraphs (65) are merged (38) by finding peer subgraphs for TS child subgraphs. TS micro-edges from module entry and to module exit are connected to peer level FSM model states or vertices identified by matching Input/Output sequences. This merging (38) is repeated until all TS child subgraphs are merged into TS childless subgraphs. TS childless subgraphs are Merged TS graphs (39).

Method and apparatus for merging hierarchical test subsequence and

A measurement of the distinctness of Finite State Machine (FSM) (33) model state transitions can expedite identification of Unique Input/Output Sequences (UIO) (63). The Input/Output (I/O) sequences associated with FSM model (33) state transitions are compared. Each different I/O sequence is replaced by a different label so that transitions with the same I/O sequence have the same label and transitions with different I/O sequences have different labels. A transformation of the count of the number of times that each label is found in the FSM model, or a subset thereof, is determined, and assigned to each corresponding transition as a Distinctness Measurement (58). This Distinctness Measurement can be used to expedite a depth-first search for Unique Input/Output Sequences (63).

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