International Business Machines Corporation

Intel Corporation

Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Semiconductor Manufacturing International Corp.

Wayfair LLC

N.s. International Ltd.

Inte Corporation

Xiao Mei Zheng

Arun Hampapur

Xuan Liu

Ajay Ashok Deshpande

Yingjie Li

Kun Tian

Christopher Scott Milite

Alan Jonathan King

Yao Zu Dong

Jae-Eun Park

Hongliang Fei

Dahai Xing

Miao He

Songhua Xing

Kimberly D Hendrix

JoAnn Piersa Brereton

Ding Ding Lin

Vadiraja S Ramamurthy

Steve Igrejas

Joline Ann Villaranda Uichanco

Rajesh M Sankaran

Tao Wang

Sanjay Kumar

Ashok Raj

Saurabh Gupta

Ali Koc

Brian Leo Quanz

Chek Keong Tan

Xian Dong Meng

Hao Ni

Arul Krishna

Na Fei Yang

Pradyumnha Gopalkrishna Kowlani

Josh Yang

Shicong Zhou

Guangyan Luo

Huang Rui

Saumil Satish Wagle

Changwei Yin

Edward Yu

Michael Yang

Chen Ji

Ethan Hoang To

The present disclosure is related to reducing shake and vibration in Head-Up Displays (HUDs) under dynamic operating conditions. The apparatus includes a curved mirror for projecting an image from a display unit on a windshield of a vehicle. The curved mirror has damping tape on its nonreflective side to absorb vibrational energy and shift the first natural frequency of the curved mirror to a higher frequency. The damping tape includes at least a viscoelastic adhesive layer and a constraining layer. The method for stabilizing the HUD includes applying damping tape selected and positioned to reduce vibrational amplitude and shift the first natural frequency of the curved mirror to a higher frequency.

Head-up display dynamic image stabilization

In an approach a computer receives a first request from a metadata service to store metadata for a virtual machine (VM). The computer validates the metadata service. The computer stores the metadata for the VM in response to the validation being successful. The computer receives a second request from the VM for the metadata. The computer sends the metadata to the VM.

Metadata service provisioning in a cloud environment

Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

Address space identifier management in complex input/output virtualization environments

Data reading method, device, and storage medium of a non-volatile memory are provided. The method includes obtaining address information and decoding the address information to determine an address of a corresponding memory cell; when the address of the memory cell is in a selected region, adjusting a first determination reference value to obtain a second determination reference value; applying a readout current to the memory cell, and obtaining a determination current outputted by the memory cell; and comparing a value range of the determination current outputted by the memory cell with the second determination reference value and reading out data content stored in the memory cell.

Data reading method, device, and medium of non-volatile memory

An apparatus and method are described for implementing a hybrid layer of address mapping for an IOMMU implementation. For example, one embodiment of a graphics processing apparatus comprises: virtualization circuitry to implement a virtualized execution environment in which a plurality of guest virtual machines (VMs) are to execute and share execution resources of the graphics processing apparatus; an input/output (I/O) memory management unit (IOMMU) to couple the VMs to one or more I/O devices; a hybrid layer address mapping (HLAM) module to combine entries from a per-process graphics translation table (PPGTT) with entries from a global graphics translation table (GGTT) into a first integrated page table, the first integrated page table mapping PPGTT guest page numbers (GPNs) to host page numbers (HPNs) and mapping GGTT virtual GPNs to HPNs; the HLAM to transform a GGTT GPN into a virtual GPN usable to access a corresponding HPN within the first integrated page table in response to a GGTT read/write operation generated by a first guest virtual machine (VM).

Apparatus and method for a hybrid layer of address mapping for a virtualized input/output (I/O) implementation

A simulator is configured to simulate the fulfillment of orders by nodes. Each node has an inventory of products and is capable of shipping the products to destinations in response to receipt of a corresponding order. The simulator divides the nodes into groups and assigns a different priority to each group based on input provided by a user to the simulator to generate an ordered sequence of priorities. The simulator maintains safety stock data corresponding to each node that indicates minimum quantities of the products required to be present at the corresponding node. The simulator selects a current priority of the sequence and next simulates a first group among the groups having the current priority fulfilling the orders for a given product among the products while a quantity of the given product at each of the nodes in the first group is below the minimum quantity in the corresponding safety stock data.

Big data sourcing simulator

Examples of techniques for generating an inter-store inventory transfer are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include defining a subset of stores of a plurality of stores to fulfill inter-store inventory transfer request for a product category of a plurality of product categories. The method may further include, responsive to determining that an order for a product of the product category cannot be fulfilled by one of the stores of the subset of stores of the plurality of stores, determining, by a processing device, an alternate store of the subset of stores to fulfill the order.

Inter-store inventory transfer

A method, system and computer program product for managing an order in an Omni-channel order fulfillment system is disclosed. A stock-keeping unit (SKU) node level cost is predicted for a plurality of SKUs. The order is received containing one or more SKUs. A candidate list of fulfillment nodes is determined for fulfilling each of the one or more SKUs in the order using the predicted SKU node level cost and a fulfillment node-destination shipping distance. One or more fulfillment nodes are selected from the candidate list, and the order is fulfilled using the selected one or more fulfillment nodes.

Two phase predictive approach for supply network optimization

In several embodiments, a graphics processor couples to a virtual machine monitor (VMM) to present a virtual graphics processor to one or more virtual machines. A mediator for the virtual graphics processor synchronously shadows modifications to a guest graphics translation table (GTT) of a virtual machine to a shadow GTT of the VMM using trap and emulate virtualization. If the mediator detects a frequency of modifications to the guest GTT that exceeds a threshold the mediator may then asynchronously shadow at least a portion of the guest GTT to the shadow GTT and rebuild the shadow GTT prior to submitting commands for the virtual graphics processor to the graphics processor.

Hybrid on-demand graphics translation table shadowing

A selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor.

Selected gate driver circuit in memory circuits, and control device and control method thereof

Various embodiments provide voltage regulator circuitry and devices. An exemplary voltage regulator circuitry can include a current comparing unit configured to convert an output voltage from a charge pump to a current and to compare the current with at least two different reference currents to generate a comparison result. A logic controller can be configured to generate a clock frequency adjustment signal based on the comparison result. A programmable clock unit can be configured to adjust a frequency of a clock signal according to the clock frequency adjustment signal to send the clock signal to the charge pump. Accordingly, the disclosed voltage regulator device can have reduced power consumption and improved reliability.

Voltage regulator devices and voltage regulating method

Growing community of inventors

Beijing, China

Xiao Mei Zheng