Micron Technology Incorporated

Battelle Energy Alliance, LLC

Xiao Li

Jaspreet Singh Gandhi

Sameer S Vadhavkar

Jian Li

James M Derderian

Steven K Groothuis

Shijian Luo

Jordan D Greenlee

Bradley R Bitz

Rita J Klein

David R Hembree

Shuangqiang Luo

Brent Keeth

Lifang Xu

Nancy M Lomeli

Anilkumar Chandolu

Luke G England

Paul A Silvestri

Andrew M Bayless

Haojun Zhang

John David Hopkins

Indra V Chary

Everett Allen McTeer

Jiewei Chen

Carla L Christensen

Benjamin L McClain

Vinayak Shamanna

Libo Wang

Jun Fang

Shen Hu

Anshika Sharma

Bethany M Grentz

Pei Qiong Cheung

Dong Wang

Kaiming Luo

Sumana Adusumilli

Chunhua Yao

Priya Vemparala Guruswamy

Cipriana Forgy

Vladimir Samara

Da Xing

Xiao Zeng

Owen R Fay

Thomas Arthur Figura

Allen McTeer

John Mark Meldrim

Tim J Corbett

Anish A Khandekar

Alyssa N Scarbrough

Shams U Arifeen

Silvia Borsari

Jivaan Kishore Jhothiraman

Jeffery B Hull

Hung-Wei Liu

Koustav Sinha

Christopher Glancey

Zhiqiang Xie

Amy R Griffin

Andy E Hooper

Naiming Liu

Maria Pat F Chavarria

Josh D Woodland

Corey Staller

Te-Sung Wu

Mohadeseh Asadolahi Baboli

Alpha Chavez Labiano

James M Dedderian

A microelectronic device comprises a stack structure, a contact structure, a liner material, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The contact structure extends through the stack structure. The liner material is between the stack structure and the contact structure. The boron-containing material is between the liner material and the stack structure. Related electronic systems and methods are also described.

Microelectronic devices comprising a boron-containing material, and related electronic systems and methods

An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

Apparatuses including interconnect structures including dielectric material surrounded by conductive material, and related memory devices

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A size comparison system may generate a size comparison by determining a size of an item based on extracted size data corresponding to the item. A comparison item is selected and the size comparison is generated between the item and the comparison item based on the size of the item. A visual rendering of the item and the comparison item is generated based on the size comparison and is displayed to a user.

Size comparison methods including online commerce examples utilizing same

Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

Systems for weather sensing and forecasting, and associated devices and methods, are disclosed herein. In some embodiments, a system for predicting a subject's perception of weather conditions is provided. The system can generate an individual profile for the subject, the individual profile including health information of the subject. The system can receive weather data including a first weather condition for a target location. The system can compare the individual profile to a plurality of different user profiles to identify one or more similar user profiles. Each similar user profile can (1) be associated with a user having similar health information as the subject, and (2) include weather perception data indicating how the user perceived a set of second weather conditions. Based on the weather data and the similar user profile(s), the system can generate a prediction of the how the subject will perceive the first weather condition.

Systems for generating personalized and/or local weather forecasts

Apparatuses including a conductive contact including a dielectric material surrounded by a conductive material

A microelectronic device having a stack structure with an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks has a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure has staircase structures each having steps with edges of the tiers of the stack structure. The filled trench has a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures have first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions that the first protrusions. Memory devices, electronic systems, and methods are also described.

Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems

Methods and apparatuses associated with surface cleaning are described. Examples can include detecting at a processing resource of a robot and via a temperature sensor of the robot, a temperature of a surface on which the robot is located. Examples can include the processing resource shutting down the robot in response to the temperature being at or above a particular threshold temperature, and the processing resource instructing the robot to clean the surface following a particular cleaning path using a vacuum, a scrubber, or both in response to the temperature being below a particular threshold temperature.

Surface cleaning

Systems, methods, and apparatus related to cruise control for a vehicle. In one approach, speed for a first vehicle is controlled in a first mode using data from sensors. The speed is controlled while keeping at least a minimum distance from a second vehicle being followed by the first vehicle. In response to determining that data from the sensors is not usable to control the first vehicle (e.g., the data cannot be used to measure the minimum distance), the first vehicle changes from the first mode to a second mode. In the second mode, the first vehicle maintains a constant speed and/or obtains additional data from sensors and/or computing devices located externally to the first vehicle. In another approach, the additional data can additionally or alternatively be obtained from a mobile device of a passenger of the first vehicle. The additional data is used to maintain a safe minimum distance from the second vehicle.

Dual-mode cruise control

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.

Semiconductor die assemblies having molded underfill structures and related technology

A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure.

Growing community of inventors

Boise, ID, United States of America

Xiao Li