Ramtron International Corporation

Texas Instruments Corporation

Xiao Hong Du

Jarrod Eliason

Yunchen Qiu

Bill Kraus

Dennis C Young

The signal margin of a small array 2T/2C memory is increased by writing the ferroelectric load capacitors on the bit lines to complementary states. A ferroelectric memory array includes rows and columns of 2T/2C memory cells, wherein each column of the memory array includes a first memory subcell having a first node coupled to a word line, a second node coupled to a first bit line, and a third node coupled to a first plate line, the first memory cell being poled in a first direction; a second memory subcell having a first node coupled to the word line, a second node coupled to a second bit line, and a third node coupled to the first plate line, the second memory cell being poled in a second direction; a first load subcell having a first node coupled to the word line, a second node coupled to the first bit line, and a third node coupled to a second plate line, the first load cell being poled in the first direction; and a second load subcell having a first node coupled to the word line, a second node coupled to a second bit line, and a third node coupled to the second plate line, the second load cell being poled in the second direction.

2T/2C ferroelectric random access memory with complementary bit-line loads

A power-on reset circuit includes a first PNP transistor having an emitter, a base, and a collector coupled to ground; a second PNP transistor having an emitter coupled to the base of the first transistor, and a base and collector coupled to ground; a third PNP transistor having an emitter, a base coupled to the base of the first transistor, and a collector coupled to ground; a first resistor coupled between VDD and an internal node; a second resistor coupled between VDD and the emitter of the first transistor; a third resistor coupled between the internal node and the emitter of the third transistor; and a comparator having a first input coupled to the internal node and a second input coupled to the emitter of the first transistor for generating a power-on reset signal.

Fast power-on detect circuit with accurate trip-points

An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n&#x2212;1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.

Imprint-free coding for ferroelectric nonvolatile counters

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN) to charge a boosting capacitor (C) to VDD at the end of each memory access and includes a PMOS FET (MP, MP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN) is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP, MP) is shorted to its source to turn if off during boostenig. Transistor (MP) facilitates boosting the NMOS FET (MN) above VDD.

CMOS voltage booster circuits

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN) to charge a boosting capacitor (C) to VDD at the end of each memory access and includes a PMOS FET (MP, MP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN) is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP, MP) is shorted to ists source to turn if off during boostenig. Ttransistor (MP) facilitates boosting the NMOS FET (MN) above VDD.

CMOS voltage booster circuit

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN) to charge the boosting capacitor (C) to VDD at the end of each memory access and to use a PMOS FET (MPMP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

A bit-line shielding technique for a ferroelectric memory logically divides the bit-lines in the array into two groups. When the bit-lines in one of the groups are accessed, the bit-lines in the other group are not accessed and thus can be grounded to electrically shield the bit-lines being accessed. Each group of bit-lines is coupled to the drains of a group of pre-charge devices at the bottom of the array. The sources of the pre-charge devices are grounded. The word lines are arranged so that only the bit-lines in one of the groups are accessed at a time.

Bit-line shielding method for ferroelectric memories

An implementation of 1T/1C nonvolatile ferroelectric RAMS without using any reference cells&mdash;the polarization state in a memory cell is determined by applying two consecutive plate pulses on the ferroelectric capacitor in the memory cell, preamplifying the bit line voltages corresponding to these two plate pulses, and comparing the preamplified voltages. The two consecutive plate pulses have the same polarity.

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Colorado Springs, CO, United States of America

Xiao Hong Du