Realtek Semiconductor Inc.

Xiao-Guo Zheng

Feng-Cheng Chang

Wei-Xiong He

The present disclosure discloses a signal receiving apparatus having parameter optimization mechanism. A signal processing circuit processes a data signal according to at least one equalization parameter to generate an equalized data signal. A clock data recovery circuit performs clock data recovery on the equalized data signal according to a primary sampling signal and a primary threshold value to generate primary recovered data. A multi-sampling circuit performs clock data recovery on the equalized data signal according to secondary sampling signals and secondary threshold values to generate a plurality of pieces of secondary recovered data. A parameter optimization circuit performs comparison and statistics on the primary recovered data and the secondary recovered data to generate an analysis result to control the signal processing circuit to adjust the equalization parameter according to the analysis result and a predetermined optimized parameter requirement such that the analysis result approximates the predetermined optimized parameter requirement.

Signal receiving apparatus and method having parameter optimization mechanism

A test system includes a transmitter, capacitor, and receiver. The transmitter includes: an output circuit coupled to the receiver via the capacitor; a transmitting circuit transmitting a predetermined signal to a pad of the output circuit during a first test; a signal generator outputting a first signal and second signal to the pad during a first process and second process of a second test; and a comparator comparing the pad's signal with a reference signal in the first process and second process to determine whether the second test passes. The receiver includes: an input circuit coupled to the transmitter via the capacitor; a switch coupled between the input circuit and a receiving circuit to be conducting in the first test and second process and nonconducting in the first process; and the receiving circuit determining whether the first test passes according to the predetermined signal and assisting the capacitor in discharging.

Test system, transmitting device, and receiving device capable of performing multiple tests in AC coupling mode

The present disclosure provides a crystal-less clock and data recovery (CDR) circuit and a frequency detection method thereof. The CDR circuit includes a clock generator and a frequency detection module. The clock generator is operable to generate a clock signal. The frequency detection module coupled to the clock generator is configured for outputting a control signal to the clock generator to increase or decrease the frequency of the clock signal according to a data signal received and a transition density.

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Suzhou, China

Xiao-Guo Zheng