Intel Corporation

Other

Xiao Dong Lin

Yong Wu

Xueliang Zhong

Jianhui Li

Yihua Jin

Jian Ye Chen

Tingtao Li

Wen Tan

Yao Zu Dong

Zhen Zhou

Shoumeng Yan

Bin Yang

Xiaoli Liu

Jiajia Yu

Shujiang Zhang

Jiong Gong

Haihao Shen

Yanling Li

Xiuqiang Zhang

A method and apparatus for keeping statistical inference accuracy with 8-bit winograd convolution. A calibration dataset and a pretrained CNN comprising 32-bit floating point weight values may be sampled to generate an input activation tensor and a weight tensor. A transformed input activation tensor may be generated by multiplying the input activation tensor and an input matrix to generate a transformed input activation tensor. A transformed weight tensor may be generated by multiplying the weight tensor and a weight matrix. A scale factor may be computed for each transformed tensor. An 8-bit CNN model including the scale factors may be generated.

Method and apparatus for keeping statistical inference accuracy with 8-bit Winograd convolution

Pet box cover

Waterproof vibrating speaker

Toy car

Water gun

An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

Efficient address translation

Stadium light

One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

Method, systems and apparatuses may provide for technology that divides an application into a plurality of portions that are each associated with one or more functions of the application and determine a plurality of transition probabilities between the plurality of portions. Some technology may also receive at least a first portion of the plurality of portions, and receive a relation file indicating the plurality of transition probabilities between the plurality of portions.

Scenario profile based partitioning and management of application code

Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

Nested emulation and dynamic linking environment

Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.

System and method for execution of application code compiled according to two instruction set architectures

Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation cache together and restore a translation cache snapshot as a whole. Chaining between translations may be maintained during saving and restoration.

Cache closure and persistent snapshot in dynamic code generating system software

Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

Multiple processor modes execution method and apparatus including signal handling

A handheld electronic game device shaped as a toy gun with two handles and two triggers, and one or more built-in display screens. The device may be played as a stand-alone device, or played with an external game unit having a display screen. When played with an external unit, the handheld device and the external unit may be provided with an aiming relationship detection system to detect an aiming of the handheld device with respect the display screen of the external unit. In one example, the screen of the external unit displays a terrain or a scene seen by the player, and the built-in display of the handheld device simulates a view seen through a scope used on traditional guns. An additional display screen may be provided on the handheld device to simulate a radar scan or satellite image.

Growing community of inventors

Shanghai, China

Xiao Dong Lin