Texas Instruments Corporation

Xianzhi Dai

Muhammad Yusuf Ali

Farzan Farbiz

Antonio Gallerano

Rajkumar Sankaralingam

A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.

Transient triggered active FET with surge immunity

A semiconductor device has a protected node and a reference node, and a bi-directional ESD structure electrically coupled between the protected node and the reference node. The bi-directional ESD structure includes a main transistor electrically coupled between the protected node and the reference node, an upper control transistor with current nodes electrically coupled between the protected node and a control node of the main transistor, and a lower control transistor with current nodes electrically coupled between the reference node and a control node of the main transistor. The bi-directional ESD structure also includes an upper trigger network configured to provide a transient on-state signal to the upper control transistor from a positive electrical pulse on the protected node. The bi-directional ESD structure further includes a lower trigger network configured to provide a transient on-state signal to the lower control transistor from a negative electrical pulse on the protected node.

Area-efficient bi-directional ESD structure

An electrostatic discharge (ESD) protection circuit includes an active shunt transistor, a first pull-down transistor, and a second pull-down transistor. The active shunt transistor is coupled between a first I/O pad and a reference voltage. The first pull-down transistor is connected to the reference voltage. The second pull-down transistor is connected to the first pull-down transistor and the first I/O pad. The first pull-down transistor and the second pull-down transistor are in separate isolation tanks of an isolation deep n-well.

Dynamically triggered electrostatic discharge cell

An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.

Growing community of inventors

Shanghai, China

Xianzhi Dai