C-sky Microsystems Co., Ltd.

Alibaba Group Holding Limited

Xianshao Chen

Aiyong Ma

Yucan Gu

Jie Wang

Peng Jiang

Bo Sun

Jiuchao Cui

Baolin Xia

Jiaqi Zhu

The present disclosure provides an off-chip memory address scrambling apparatus and method for a system on chip. The apparatus includes a true random number generator, a key memory and an on-chip security controller. The on-chip security controller is connected to the true random number generator, the key memory and an off-chip memory respectively and is configured to read or write data in the off-chip memory and perform address scrambling processing on the data. The on-chip security controller includes: a memory interface module, and an address scrambling module configured to read a random key stored in the key memory, to select according to a valid/invalid state of the random key to directly invoke the read random key or read again a random key that is generated by the true random number generator and stored into the key memory, and then to perform according to the random key scrambling algorithm processing on an unscrambled address inputted by the memory interface module to form a scrambled address, and output the scrambled address to an address scrambling module of the off-chip memory. The present disclosure can improve the security while high efficiency.

Off-chip memory address scrambling apparatus and method for system on chip

Embodiments of the disclosure provide a method and apparatus for upgrading a system version of a system. The method can include: acquiring, using circuitry, from a first storage space a current system version identification corresponding to a current system version; acquiring, using circuitry, from a second storage space a backup system version identification corresponding to a backup system version; comparing, using circuitry, the current system version identification with the backup system version identification; and configuring the system based on the comparison.

System version upgrading method and apparatus

Provided is a bitwise writing apparatus for a SOC system. The apparatus includes a slave device interface module, a decoding module and a master device interface module. The slave device interface module is configured to receive a write request sent by a master device interface of a bus controller and send the write request to the decoding module. The decoding module is configured to receive the write request sent by the slave device interface module, decode the write request and send valid information after the decoding to the master device interface module. The master device interface module is configured to receive the valid information sent by the decoding module, read data in a destination address, perform a bitwise operation for the read data to obtain new data, send a write request to a slave device interface of the bus controller and write the obtained new data into a peripheral register corresponding to the destination address. The system can effectively reduce the instruction storage space and thereby reduce the chip area and lower the chip cost.

Bitwise writing apparatus for system-on-chip system

Growing community of inventors

Hangzhou, China

Xianshao Chen