Boe Technology Group Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Xianrui Qian

Bo Li

Yuting Chen

Zixuan Wang

Fei Fei Li

Peng Chen

Tong Yang

Suzhen Mu

Guolei Wang

Xiong Xiong

Donghui Zhang

Zhou Rui

Yunlong Cai

A shift register unit circuit includes an input sub-circuit, a pull-up sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, and a voltage regulating sub-circuit. The input sub-circuit receives an input signal from a signal input terminal to control a potential of a pull-up node. The pull-up sub-circuit outputs a gate driving signal to an output terminal under control of the potential of the pull-up node and a signal from a first signal terminal. The pull-down control sub-circuit conducts a pull-down node with a first node under control of a signal from the second signal terminal. The pull-down sub-circuit conducts the pull-up node with the first node and the turn-down signal terminal with the output terminal under control of a potential of the pull-down node. The voltage regulating sub-circuit conducts the first node with the turn-down signal terminal under control of a potential of the first node.

Shift register unit circuit and driving method, shift register, gate drive circuit, and display apparatus

The present disclosure provides a pixel driving circuit, a driving method thereof, and a display device, and relates to the field of display technology. The pixel driving circuit includes a first driver, a second driver, and a light emitting element. The first driver is configured to generate a first driving current. The second driver is configured to generate a second driving current. The first driving current and the second driving current alternately drive the light emitting element as a main driving current.

Pixel driving circuit, driving method thereof, and display device

A shift register circuit includes a pull-up control sub-circuit, a pull-up sub-circuit and a shutdown auxiliary sub-circuit. The pull-up control sub-circuit is configured to transmit a voltage from the signal input terminal to the pull-up node under the control of the voltage from the signal input terminal. The shut-down auxiliary sub-circuit is configured to pull down a voltage of the pull-up node to a voltage of the discharge voltage terminal under the control of a voltage from the pull-up node. The pull-up sub-circuit is configured to transmit a voltage from the clock signal terminal to the first signal output terminal under the control of a voltage from the pull-up node. The first signal output terminal is configured to be connected to a gate line.

Shift register circuit and method of controlling the same, gate driving circuit, and display device

A shift register circuit includes a noise reduction sub-circuit and a pull-down node control sub-circuit. A control end of the noise reduction sub-circuit is connected to a pull-down node, the noise reduction sub-circuit is connected to a first voltage input end. The pull-down node control sub-circuit includes a first pull-down node control sub-circuit and a second pull-down node control sub-circuit. The second pull-down node control sub-circuit controls the pull-down control node to be connected to a first clock signal input end when the first clock signal input end inputs a first level, the pull-down node to be connected to the first clock signal input end when a potential of the pull-down control node is at the first level, so that the potential of the pull-down node is at a first level and a noise reduction transistor included in the noise reduction sub-circuit is turned off.

Shift register circuit, method for driving the same, and display device

There is provided in the present disclosure a shift register unit, including: a pull-up control circuit, connected to a signal input terminal and a pull-up node; a pull-up circuit, connected to the pull-up node, a first clock signal terminal and a signal output terminal; a pull-down circuit, connected to a pull-down node, the pull-up node, the signal output terminal and a power supply voltage terminal, and configured to pull down voltages of the pull-up node and the signal output terminal to a voltage of the power supply voltage terminal under the control of the pull-down node; a first pull-down control circuit, connected to a second clock signal terminal, a pull-down control signal terminal, the pull-down node and the power supply voltage terminal, and configured to pull up the voltage of the pull-down node to a valid pull-down level under the control of the pull-down control signal terminal.

Shift register unit and driving method thereof, driving apparatus and display apparatus

The embodiments of the present application provide a shift register, a method for controlling the same, a gate driving circuit, and a display apparatus. The shift register includes: an input circuit coupled to a signal input terminal and a pull-up node; a pull-up circuit coupled to the pull-up node, a first clock signal terminal and a signal output terminal; a pull-down circuit coupled to a reset signal terminal, a first voltage signal terminal, the pull-up node, and the signal output terminal; a pull-down control circuit coupled to a second clock signal terminal, the pull-up node, a pull-down node, and the first voltage signal terminal; a first de-noising circuit coupled to the pull-up node, the signal input terminal, the first voltage signal terminal, and a compensation node; and a compensation circuit coupled to the first clock signal terminal, the second clock signal terminal, and the compensation node.

Shift register, method for controlling the same, gate driving circuit and display apparatus

The present disclosure relates to a pixel driving circuit and a driving method for the same and a display panel. The pixel driving circuit includes a driver unit, a circuit switching unit, and a storage capacitor unit. The driver unit includes a first sub-driver unit and a second sub-driver unit. The circuit switching unit has a first switching unit and a second switching unit. Two terminals of the first switching unit are electrically connected to a first terminal of the light emitting unit and the first sub-driver unit, respectively, two terminals of the second switching unit are electrically connected to the light emitting unit and the second sub-driver unit, respectively, and the circuit switching unit is configured to switch conductive states of the first switching unit and the second switching unit.

Pixel driving circuit having dual driver unit, driving method for the same and display panel

A pixel circuit includes a first control sub-circuit, a second control sub-circuit, a current detection sub-circuit, a driving sub-circuit, and an energy storage sub-circuit. The first control sub-circuit is configured to transmit a voltage on a data voltage terminal to a first node under control of a voltage on a first scan signal terminal. The second control sub-circuit is configured to transmit the voltage on the first node to a control terminal of the driving sub-circuit under control of a voltage on a second scan signal terminal. The current detection sub-circuit is configured to output a detection current under control of the voltage on the first node and detect a current value of the detection current. The driving sub-circuit is configured to output a driving current under control of the voltage on the control terminal of the driving sub-circuit. The energy storage sub-circuit is configured to store electrical energy.

Pixel circuit and drive method thereof, and display panel and display device

A shift register, an array substrate and a display device in the field of display technology are provided in the present disclosure. In the shift register, the gate electrode of the first transistor is connected to a second node, one of the source electrode and the drain electrode is connected to a first clock signal line, and the other one is connected to the first node. The gate electrode of the second transistor is connected to the second node, one of the source electrode and the drain electrode is connected to the second node, and the other one is connected to the first clock signal line. The charging circuitry is configured to set the second node to an effective level when a second clock signal line is at an effective level. The memory circuitry is configured to store the threshold voltage of the second transistor and compensate the threshold voltage of the first transistor with the stored threshold voltage.

Shift register, array substrate and display device

A display device, a gate drive circuit, a shift register and its control method are described. The shift register includes: an input circuit, a first output circuit, a second output circuit, a control circuit and an output drive circuit, wherein the output drive circuit is connected to a second signal input terminal, a pull-up node, a control terminal of the second output circuit and a low voltage signal terminal, and is configured to write a voltage of the second signal input terminal into the control terminal of the second output circuit and superimpose a voltage of the pull-up node onto the control terminal of the second output circuit under the control of a second input signal provided at the second signal input terminal, such that the second output circuit is fully turned on to ensure that it has good output capability when working at a low temperature.

Display device, gate drive circuit, shift register and control method for the same

A pixel driving circuit, a driving method, an organic light emitting display panel and a display device, including: a data writing module, a storage module, at least one first light emitting device, a first driving module corresponding to the respective first light emitting device one-to-one, at least one second light emitting device, and a second driving module corresponding to the respective second light emitting device one-to-one.

Pixel driving circuit, driving method, organic light emitting display panel and display device

Provided are a shift register and a driving method thereof, a gate on array circuit and a display apparatus. The shift register includes a pre-charging module, an output module, a reset module and a reset control module. The pre-charging module is configured to charge a first node in a pre-charging period. The output module is configured to pull up a voltage at the first node and output a driving signal through the output signal terminal in an output period. The reset control module is configured to pull up a voltage at the second node by the driving signal outputted through the output signal terminal in the output period and output the voltage at the second node pulled up in the output period to the reset module as a reset signal in a reset period.

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Beijing, China

Xianrui Qian