Suzhou Metabrain Intelligent Technology Co., Ltd.

Inspur Suzhou Intelligent Technology Co., Ltd

Xiankun Wang

Tuo Li

Yulong Zhou

Tongqiang Liu

Hongtao Man

Xiaofeng Zou

Zhenlei Zhang

Disclosed in the present disclosure are a video compression system and a server. The video compression system includes a Central Processing Unit (CPU), a hardware detection module, a write control module, a read control module, and an First In First Out (FIFO) array module; the CPU is configured to send a first enable signal to the hardware detection module, the read control module, and the selection switch; the selection switch is configured to select to write test data into the FIFO array module through the hardware detection module based on the first enable signal; the hardware detection module is configured to write test data into the FIFO array module based on the first enable signal; and the read control module is configured to read the test data from the FIFO array module based on the first enable signal and transmit the test data to the hardware detection module.

Video compression system and server

The present application discloses method for transmitting video data, applied to chip for substrate management control. The method includes: respectively storing video compression data into first storage space and second storage space according to ping-pong operation structure; reading data of the same byte length from the first storage space and the second storage space; determining whether similarity between first data to be transmitted and second data to be transmitted is greater than or equal to preset value; if yes, setting the first data to be transmitted added with first transmission identifier as the current frame of data, and setting a second transmission identifier corresponding to the first transmission identifier as the next frame of data; and sending the current frame data and the next frame data to video data receiving end.

Video data transmission method, video data decoding method, and related apparatuses

Provided is a FPGA-based design method for equally dividing an interval, including the following steps: dividing the oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by the number of equally divided sampling pulses, and obtaining the remainder thereof; dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; using a counter to count from the second pulse, and stopping the counting of the counter once whenever the error within the sampling interval, which is accumulated within the second pulse interval, is greater than or equal to the vibration period. Further provided is a FPGA-based design device for equally dividing an interval. The present application makes full use of the feature of interval equal division calculation, has high precision, and is easy to implement.

FPGA-based design method and device for equally dividing interval

Growing community of inventors

Jiangsu, China

Xiankun Wang