Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Xiankun Jin

Tao Chen

Jan-Peter Schat

Douglas Alan Garrity

Robert S Jones, Iii

Kumar Abhishek

Mark Lehmann

Srikanth Jagannathan

Chris C Dao

Mark Stachew

Kushagra Bhatheja

Lei Ma

Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.

Testing of on-chip analog-mixed signal circuits using on-chip memory

Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

Compensated alternating polarity capacitive structures

An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.

Apparatuses involving calibration of input offset voltage and signal delay of circuits and methods thereof

An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.

Systems and methods for detecting faults in an analog input/output circuitry

Body text indent&#x2014;does not have paragraph numbering turned on. Not needed in the Abstract. An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.

Analog-to-digital converter (ADC) testing

In an integrated circuit, a bootstrapped switch includes a capacitor and first, second, and third transistors. The first transistor has a first current electrode coupled to a first voltage supply node and a gate electrode coupled to a first circuit node. The second transistor has a first current electrode coupled to a second voltage supply terminal, a second current electrode coupled to a top terminal of the capacitor, and a control electrode coupled to the first circuit node. The third transistor has a first current electrode coupled to the first voltage supply terminal, a control electrode coupled to the first circuit node, and a second current electrode coupled to a body terminal of the second transistor. The fourth transistor has a first current electrode coupled to the body terminal of the second transistor, and a second current electrode coupled to the top terminal of the capacitor.

Bootstrapped switch

An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.

Analog-test-bus apparatuses involving calibration of comparator circuits and methods thereof

A self-test apparatus for use in an electronic system includes an inter-chip communication bus, a plurality of circuit devices, circuitry including memory, and test controller circuitry. The plurality of circuit devices each has a distributed self-test controller circuit and analog, mixed signal or digital circuit elements. The distributed self-test controller circuits are integrated communicatively via the inter-chip communication bus and negotiate a self-test protocol with each other. The circuitry including memory stores self-test properties of the circuit elements, the self-test properties corresponding to an identifier of each of the circuit elements and a manner or protocol in which the circuit elements are tested. The test controller circuitry collects the self-test properties of the circuit elements and controls execution of the self-test according to the negotiated self-test protocol and the self-test properties.

Self-test apparatuses having distributed self-test controller circuits and controller circuitry to control self-test execution based on self-test properties and method thereof

A dynamic comparator includes two sets of input transistors of opposite conductivity types, where a control electrode of one transistor of each set is coupled to a first input of the comparator and a control input of a second transistor of each set is coupled to a second input of the comparator. The comparator includes bypass transistors for pulling current electrodes of either the first set or second set of input transistors to a power supply terminal depending which input voltage is higher as determined by the output.

Dynamic comparator

Analog-to-digital conversion is tested in-field using an on-chip built-in self-test (BIST) sub-circuit formed within an underlying integrated circuit. Processing cycles may be conscripted during an idle state when the analog-to-digital conversion is not needed. The BIST requires a test time which may be compared to an idle time. If the idle time exceeds the test time, then the BIST may be entirely performed. However, if the idle time is unknown or less than the test time, the BIST may be paused and resumed between subsequent idle states.

Built-in self test for A/D converter

An on-chip built-in self-test (BIST) circuit () uses a controller (), analog-to-digital converter (ADC) (), and digital-to-analog converter (DAC) () to sense voltage and/or temperature measures at predetermined circuit locations (), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus () to the analog block, and to process analog test signals received over a second bus () from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.

Non-intrusive on-chip analog test/trim/calibrate subsystem

A current source circuit includes a first variable resistor circuit. The first variable resistor circuit includes a resistive material and a first plurality of tap inputs configured to set a resistance of the first variable resistor circuit. The current source circuit includes an output configured to provide a current. The current is adjustable by varying the resistance of the first variable resistor circuit. The current source circuit includes a second variable resistor circuit. The second variable resistor circuit includes a resistive material of a same resistive material type as the resistive material of the first variable resistor circuit. The second variable resistor circuit includes a second plurality of tap inputs configured to set a resistance of the second variable resistor circuit. Each tap resistance of the second variable resistor circuit is proportional to a corresponding tap resistance of the first variable resistor circuit. A first terminal of the second variable resistor circuit is coupled to a first test port and a second terminal of the second variable resistor circuit is coupled to a second test port to allow for a resistance measurement of the second variable resistor circuit during a test mode. The current source circuit includes a non-volatile storage circuit configured to store a tap value generated during the test mode corresponding to a set of select signal values for the second plurality of tap inputs which provides a desired resistance of the second variable resistor circuit as determined during the test mode and to provide a set of select signal values for the first plurality of tap inputs based on the tap value stored in the non-volatile storage circuit.

Current source with variable resistor circuit

A data processing system having an analog-to-digital converter (ADC) and method for testing the ADC are provided. The data processing system also comprises a digital-to-analog converter (DAC) and test logic. The DAC has a first voltage range, an input for receiving a test code, and an output. The ADC has a second voltage range larger than the first voltage range, an input coupled to the output of the DAC, and an output for providing a series of output codes over the second voltage range. The test logic is coupled to the ADC and is for controlling testing of the ADC using the DAC. A plurality of series of test codes are provided to the DAC for testing portions of the second voltage range output from the ADC. A beginning series of test codes is for testing a beginning portion of the second voltage range and subsequent series of test codes are for testing subsequent portions of the second voltage range. Subsequent portions of the second voltage range are tested until a maximum voltage of the second voltage range of the ADC is reached.

Method for testing analog-to-digital converter and system therefor

A method and circuit for testing an analog-to-digital converter (ADC) are provided. The method comprises: coupling a single-ended output of an analog signal source to a differential input of an amplifier; coupling a differential output of the amplifier to a differential input of the ADC; alternately providing first and second test signals from the single-ended output of the analog signal source to first and second input terminals of the differential input of the amplifier; amplifying the first and second test signals to generate amplified differential signals at the differential output of the amplifier; providing the amplified differential signals to the differential input of the ADC; and determining if an output of the ADC is as expected. An offset may also be provided to the differential output of the amplifier. The method allows an ADC having a differential input to be tested using a digital-to-analog converter (DAC) having a single-ended output.

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Austin, TX, United States of America

Xiankun Jin