No. 24 Research Institute of China Electronics Technology Group Corporation

Xianjie Wan

Dongbing Fu

Ting Li

Gangyi Hu

Daiguo Xu

Liang Li

Mingyuan Xu

Xiaofeng Shen

Zhengping Zhang

Jie Pu

Youhua Wang

The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

Circuit for generating multi-phase clock having random disturbance added thereto

Growing community of inventors

Chongqing, China

Xianjie Wan