Qualcomm Incorporated

Google Inc.

Xiangyu Dong

Jungwon Suh

Jung Pill Kim

Deepti Vijayalakshmi Sriramagiri

Jianqiao Liu

Kais Belgaied

Dexter Tamio Chun

Yanru Li

Taehyun Kim

Sungryul Kim

Mosaddiq Saifuddin

Pedram Zare Dashti

Yazhou Zu

Xiaochun Zhu

Xiao Meng Zhang

Yong Zhao

Alireza Ghaffarkhah

Dayou Du

Kexin Yang

Hoang-Vu Dang

Arash Rezaei

Xiangling Kong

Alexander Vadimovich Kolbasov

Jiafan Zhu

Jikai Tang

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for an enhanced reconfigurable interconnect network. The reconfigurable interconnect network can be used to switch between multiple different connection topologies for different sizes of subsets of processing nodes in a cluster. For example, for a given number of processing nodes to be used, different connection topologies can provide different levels of scalability, data transfer bandwidth among processing nodes, and latency for transfers among processing nodes. In some implementations, the connection topologies can assign connections for each of the data ports of the processing nodes used, to maximize utilization of the data ports and provide better performance.

Enhanced reconfigurable interconnect network

Methods, systems, and apparatus, including computer programs encoded on computer storage media for performing preflight checks of a distributed computing system, are described. In one aspect, a method includes assigning a computing workload to a first subset of hardware accelerator machines each having one or more hardware accelerators. A preflight check on the first subset is performed before performing the computing workload to verify the functionality of each machine in the first subset. For each hardware accelerator machine of the first subset, a program code package is installed, including a task action based at least in part on characteristics of the computing workload. The task action including a sequence of operations is performed on the hardware accelerator machine to determine whether the task action fails. Whenever the task action fails, the computing workload is re-assigned to a second subset of hardware accelerator machines different from the first subset.

Preflight checks for hardware accelerators in a distributed system

This disclosure generally provides solutions for improving the performance of a custom-built, packet-switched, TPU accelerator-side communication network. Specifically a set of solutions to improve the flow-control behavior by tuning the packet buffer queues in the on-chip router in the distributed training supercomputer network are described.

Queue allocation in machine learning accelerators

A uniform and unified firmware in-field upgrade capability for the optics modules may ensure compatibility, security and code quality, and scalability. In some examples, an intermediate representation, which includes vendor firmware upgrade operations and control logic, may be defined, received, and parsed. Read/write operations may be communicated to optical module(s) based on the control logic. In some examples, a unified optics module firmware in-field upgrade framework, which has multiple defined software layers, may ensure a uniform and unified approach to managing optics module(s) from different vendors and used by different projects. The software layers that may properly translate optics module read/write operations, abstract and make uniform the read/write operations, provide libraries of intermediate representations, package the intermediate representations into executables/scripts, monitor optics module status, determine when a new firmware is released, and gradually upgrade the optics module firmware.

Methods for optics module firmware in-field upgrade

A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.

Method and apparatus for refreshing a memory cell

A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

Method and apparatus for in-system management and repair of semi-conductor memory failure

Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information.

Method and apparatus for storing retention time profile information based on retention time and temperature

A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

DRAM sub-array level autonomic refresh memory controller optimization

Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.

Systems and methods for reducing memory failures

A hybrid cache architecture uses magnetoresistive random-access memory (MRAM) caches but has two different types of bit cell sensing. One type of bit cell sensing is single-ended and the other type of bit cell sensing is differential. The result is a uniform bit cell array but a non-uniform sense amplifier configuration.

Hybrid magnetoresistive read only memory (MRAM) cache mixing single-ended and differential sensing

A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

System and method to defragment a memory

A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.

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San Diego, CA, United States of America

Xiangyu Dong