Intel Corporation

Altera Corporation

Xiangyong Wang

Mahesh A Iyer

Ning Cheng

Brent Alan Fairbanks

XiangDong Tan

An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

Methods and apparatus for reducing reliability degradation on an integrated circuit

A method and associated computer program product is provided for determining placement of I/O pins on an integrated circuit device. In an exemplary embodiment, a set of pins to be placed is partitioned into pin groups prior to placing individual pins. After partitioning the pins into pin groups, pin groups may, in a preferred embodiment, be ranked according to difficulty of placement. Pins in the most difficult group are placed first by applying a method that, in a preferred embodiment, places pins within the limits imposed by current density requirements while achieving high pin density within those limits when pad resources are relatively limited.

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Xiangyong Wang