Marvellworld Trade Ltd.

Xiangyang Simon Xu

Cindy Chun Wang

Xiaochun Chen

A delay buffer includes a first shift register receiving input data and having a shift signal input port. The first shift register right shifts the input data responsive to a shift signal on the shift signal input port. The shift signal is determined based on an effective bit width of the input data. A first delay line receives the shifted data from the first shift register while a second delay line of equal length to the first delay line receives the shift signal. A second shift register receives the output from the first delay line and receives the output of the second delay line on a shift signal input port. The second shift register then left shifts the data contained therein according to the shift signal.

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San Jose, CA, United States of America

Xiangyang Simon Xu