Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Xiangxiang Lu

Chien-Hsin Lee

Manjunatha Govinda Prabhu

Mahadeva Iyer Natarajan

Mujahid Muhammad

Ephrem G Gebreselasie

Shunhua Thomas Chang

Mickey H Yu

Wei Gao

Tsung-Che Tsai

Vaddagere Nagaraju Vasantha Kumar

High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Transistors patterned with electrostatic discharge protection and methods of fabrication

The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.

Apparatus and method to prevent integrated circuit from entering latch-up mode

An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.

Electrostatic discharge (ESD) protection transistor devices and integrated circuits with electrostatic discharge protection transistor devices

Integrated circuits with lateral bipolar transistors and methods for fabricating the same are provided. An exemplary integrated circuit includes a semiconductor layer overlying an insulator layer. The semiconductor layer includes a first region having a first thickness and a trench region having a second thickness less than the first thickness. The integrated circuit further includes an isolation region formed over the trench region of the semiconductor layer. Also, the integrated circuit includes a lateral bipolar transistor including a base formed in the trench region of the semiconductor layer, an emitter, and a collector.

Integrated circuits with lateral bipolar transistors and methods for fabricating the same

Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a heavily doped source area having conductivity determining impurities at a heavily doped source concentration and a lightly doped drain area having conductivity determining impurities at a lightly doped drain concentration less than the heavily doped source concentration. A drain conductor directly contacts the lightly doped drain area, and a channel is positioned between the heavily doped source area and the lightly doped drain area. A gate overlies the channel.

Integrated circuits resistant to electrostatic discharge and methods for producing the same

Integrated circuits with components for protection from electrostatic discharge are provided. An integrated circuit includes a first common line and a second common line. A first electrostatic discharge line is in electrical communication with the first and second common lines. The first electrostatic discharge line includes a first diode and a first clamping device.

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Singapore, Singapore

Xiangxiang Lu