Northrop Grumman Systems Corporation

Xianglin Zeng

Jesse B Tice

John A Starkovich

Edward M Silverman

Hsiao-Hu Peng

Patty Pei-Ling Chang-Chien

Andrew D Kostelec

Phuong Nguyen

Chunbo Zhang

Vincent Gambin

Yaochung Chen

Roger S Tsai

Melanie Sachiko Yajima

Xing Lan

Jeffrey M Yang

Jeffrey Ming-Jer Yang

Patty P Chang-Chien

Daniel R Scherrer

Kelly Jill Hennig

Kelly Jill Tornquist Hennig

Shih-En Shih

Philip W Hon

Patrick J Case

Jose G Padilla

Maria L Tenorio

Chi Kong Cheung

Kelly Jill Henning

A heat spreader for printed wiring boards and a method of manufacture are disclosed. The heat spreader is made from a plurality of graphene sheets that are thermo-mechanically bonded using an alloy bonding process that forms a metal alloy layer using a low temperature and pressure that does not damage the graphene sheets. The resulting heat spreader has a higher thermal conductivity than graphene sheets alone.

Alloy bonded graphene sheets for enhanced thermal spreaders

A sensor assembly for determining whether a hermetically sealed cavity between opposing substrate wafers in a wafer level packaged (WLP) chip is leaking. The sensor assembly includes a thermal insulating layer provided within the cavity, and a heater and temperature sensor deposited on the insulation layer. The thermal insulating layer is made of a suitable dielectric that is compatible with WLP and MMIC fabrication processes and can be, for example, benzocyclobutene (BCB) or polyimide. The sensor is responsive to a current that heats the thermal insulation layer so that heat dissipated by the thermal insulation layer is drawn away by gas between the layer and the substrate that determines the temperature of the sensor, which is detected.

Micro hermetic sensor

A method of manufacturing electronics using a nanoparticle ink printing method includes: synthesizing a phase change material (PCM) ink composition using hot injection to develop nanoparticles of the PCM; suspending the nanoparticles with a solvent; and printing a reconfigurable component using the PCM ink composition in additive manufacturing. Electronics includes: a substrate layer; an insulator layer printed on top of the substrate layer; a heater layer printed on top of the insulator layer; a barrier layer printed on top of one or more of the insulator layer and the heater layer; a phase change material (PCM) printed on top of the barrier layer; a connectivity layer printed on top of the PCM; and a passivation layer printed on top of one or more of the PCM and the connectivity layer.

Large-scale reconfigurable electronics using low cost nanoparticle ink printing method

A vertical cavity surface emitting laser (VCSEL) including a substrate and a bottom distributed Bragg reflector (DBR) having a plurality of layers deposited on the substrate. The VCSEL also includes a first charge confining layer deposited on the bottom DBR, an active region deposited on the first charge confining layer, and a second charge confining layer deposited on the active region. A current blocking layer is provided on the second charge confining layer, and a top epitaxial DBR including a plurality of top epitaxial DBR layers is deposited on the current blocking layer. A top electrode is deposited on the top epitaxial DBR, a bottom electrode is deposited on the bottom DBR and adjacent to the active region, and a top dielectric DBR is deposited on the top epitaxial DBR and the top electrode.

Vertical cavity surface emitting laser with composite reflectors

A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.

Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems

A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The plasma limiter includes a signal substrate and a trigger substrate defining a hermetically sealed cavity therebetween in which is encapsulated an ionizable gas. The signal substrate includes a signal line within the cavity and the trigger substrate includes at least one trigger probe extending from the trigger substrate towards the transmission line. If a signal propagating on the transmission line exceeds a power threshold, the gas within the cavity is ionized creating a conduction path between the transmission line and the trigger probe that draws off the high power current.

Integrated micro-plasma limiter

A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.

Wafer level packaging integrated hydrogen getter

A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling.

Method of batch integration of low dielectric substrates with MMICs

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Monterey Park, CA, United States of America

Xianglin Zeng