International Business Machines Corporation

Broadcom Corporation

Qualcomm Incorporated

Taiwan Semiconductor Manufacturing Comp. Ltd.

Freescale Semiconductor,inc.

Samsung Electronics Co., Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Inc.

Infineon Technologies North America Corp.

Avago Technologies International Sales Pte. Limited

Xiangdong Chen

Haining S Yang

Wei Xia

Venugopal Boynapalli

Sam Ziqun Zhao

Pieter Vorenkamp

Rezaur Rahman Khan

Hyeokjin Lim

Kevin Kunzhong Hu

Sampath K V Karikalan

Akira Ito

Jerry Chang Jui Kao

Geng Wang

Ohsang Kwon

Satyanarayana Sahu

Mukul Gupta

Kern Rim

Hui-Zhong Zhuang

Henry Kuo-Shun Chen

Lee-Chung Lu

Stanley Seungchul Song

Yung-Chen Chien

Foua Vang

Frank Hui

Thomas W Dyer

Dae-Gyu Park

Jae-Eun Park

Tzu-Ying Lin

Seid Hadi Rasouli

Weipeng Li

Huilong Zhu

Dureseti Chidambarrao

Qiqing Christine Ouyang

John Jianhong Zhu

Xinlin Wang

Da Zhang

Christopher V Baiocco

Melanie J Sherony

Mickael Malabry

Young Gun Ko

Chih-Liang Chen

Choh Fei Yeap

Voon-Yew Thean

Guo-Huei Wu

Kenneth Jay Stein

Young Way Teh

Deleep R Nair

Raymond George Stephany

Zhijiong Luo

Herbert Lei Ho

Brian Joseph Greene

Jung-Chan Yang

Zhongze Wang

Deok-Kee Kim

Sunfei Fang

Xiaobin Yuan

Animesh Datta

Esin Terzioglu

Yujun Li

Laegu Kang

Wei-Ling Chang

Shao-Lun Chien

Jie Deng

James J Toomey

Nam Sung Kim

Daniel K Tekleab

Renukprasad Hiremath

Oleg Gluschenkov

Haizhou Yin

Ting-Wei Chiang

Shih-Ming Chang

Chih-Wei Chang

Chandrasekharan Kothandaraman

Sheng-Hsiung Chen

Kam-Tou Sio

Ken-Hsien Hsieh

Jin Cai

Chi-Yu Lu

Chi-Lin Liu

Michael P Belyansky

Jeffrey Xu

Srikanth Balaji Samavedam

Jin-Ping Han

Agnes Woo

Yong Meng Lee

Anda C Mocuta

Rajesh Rengarajan

Ramaprasath Vilangudipitchai

Atul Champaklal Ajmera

Daewon Yang

Thomas A Wallner

Henry Chen

Dorav Kumar

Qi Ye

Kam-tou Sio

Jung-chan Yang

Li Ming Wang

Kent Charles Oertle

Jun Jung Kim

Jennifer Chiao

An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.

Integrated circuit structure and method for manufacturing the same

A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Semiconductor structure and method for forming the same

A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Semiconductor device and method of manufacturing the same

Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

Scan flip-flops with pre-setting combinational logic

Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Low hold multi-bit flip-flop

A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

Low-power flip-flop architecture with high-speed transmission gates

A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Clock gating circuit and method of operating the same

A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.

Multi-bit standard cell

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mlayer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mlayer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mlayer interconnects are parallel. The MOS device further includes a first Mlayer interconnect extending in a second direction orthogonal to the first direction. The first Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The MOS device further includes a second Mlayer interconnect extending in the second direction. The second Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The second Mlayer interconnect is parallel to the first Mlayer interconnect.

Multiple via structure for high performance standard cells

A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

Shunt power rail with short line effect

Metal oxide semiconductor device of an integrated circuit

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Irvine, CA, United States of America

Xiangdong Chen