Lattice Semiconductor Corporation

Xilinx, Inc.

Juniper Networks, Inc.

Integrated Device Technology, Inc.

Xiang Zhu

Ming Qu

Greg W Starr

Zhengyu Yuan

Xiangwen Xu

Hexin Wang

Kochung Lee

Yongmin Ge

Xueping Jiang

In one embodiment, a method includes receive a translation vector, selecting a translation entry from a plurality of translation entries, and determining whether the translation entry is associated with a first identifier class or a second identifier class. The translation vector includes a first identifier, a second identifier, and a virtual memory identifier. The first identifier is associated with a first identifier class, and the second identifier is associated with a second identifier class. The translation vector is received from a translation module including a memory configured to store the plurality of translation entries. Each translation entry from the plurality of translation entries including a virtual memory identifier. The translation entry is selected from the plurality of translation entries of the translation module based on the virtual memory identifier of the translation vector. The determining whether the translation entry is associated with the first identifier class or the second identifier class is based on a shared indicator associated with the translation entry.

Methods and apparatus for improved access to shared memory

A data link interface can include a programmable delay chain configured to provide an amount of delay to a first clock signal that clocks a first portion of a data path. The data link interface can include a phase interpolator configured to determine an amount of phase offset applied to a second clock signal that clocks a second portion of the data path. The data link interface further can include a latency detector coupled to the programmable delay chain and the phase interpolator. The latency detector can measure a phase difference between the first and second clock signals and vary the amount of delay applied to the first clock signal and/or the amount of phase offset on the second clock signal responsive to the phase difference.

Low latency transmitter path data link interface

A method and apparatus for clock phase alignment are described. An external clock is aligned to an internal clock by adjusting phase of the external clock. The external clock is of a physical medium attachment clock domain, and the internal clock is of a physical coding clock domain. After the aligning of the external clock to the internal clock, the external clock is maintained. The internal clock is aligned to the external clock by adjusting phase of the internal clock.

Clock phase alignment

Alignment of a clock signal to a particular phase is described. In one aspect, a method includes receiving an incoming clock signal and multiple phased clock signals, each of the phased clock signals having a different phase and a substantially same phase offset from another phased clock signal. At least one detection signal based on the incoming and phased clock signals is provided, and one or more errors contributed by noise in at least the incoming clock signal are corrected in the at least one detection signal. Based on the at least one detection signal, one of the phased clock signals is selected as the most closely aligned of the phased clock signals to the predetermined clock phase, and the selected clock signal is output.

Phase detection and aligned signal selection with multiple phases of clocks

An adaptive decision feedback equalizer includes a filter module, a compensation module, and a slicer module. The filter module generates a filtered signal by adaptively filtering an input serial data signal to reduce inter-symbol interference in the serial data signal. The compensation module generates a compensated signal by equalizing amplitudes of frequency components of the filtered signal in a compensation frequency range to reduce inter-symbol interference in the filtered signal. The slicer module determines logic states of serial data in the compensated signal and generates an output serial data signal including serial data having the determined logic states.

Adaptive decision feedback equalizer for high data rate serial link receiver

An integrated circuit of an embodiment may comprise synchronous logic, combinational logic, and clock circuitry to clock the synchronous logic through various states dependent on the combinational logic. The synchronous logic may comprise a plurality of master-slave registers. The combinational logic is configured to drive data inputs of the synchronous logic dependent on states established by the master-slave registers. The clock circuitry is configured to clock the master portion of the master-slave registers with a lag rendering of a clock signal and to clock the slave portion of the registers with a lead rendering of the clock signal. In a particular example, the circuitry may define a frequency divider of a complementary CMOS realization.

Integrated circuits and complementary CMOS circuits for frequency dividers

A switched-capacitor ripple-smoothing filter includes a first pair of capacitors. The filter is configured such that either capacitor in the first pair may be reset and have a terminal coupled to a first input port and such that the remaining capacitor in the first pair is isolated from the first input port and has the terminal coupled to a first output port while the other capacitor is being charged. The filter further includes a second pair of capacitors, the filter being configured such that either capacitor in the second pair may be reset and have a terminal coupled to a second input port and such that the remaining capacitor in the second pair is isolated from the second input port and has the terminal coupled to a second output port while the other capacitor in the second pair is being charged. Advantageously, the filter is configured such that the capacitors in the first and second pair are reset responsive to the assertion of a single reset signal.

Switched capacitor ripple-smoothing filter

A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.

Control signal generation for a low jitter switched-capacitor frequency synthesizer

A charge pump for a differential phase-locked loop (PLL) is provided. The charge pump includes a current switch configured to voltage to source and sink a current in a complementary fashion from a pair of differential output nodes. The charge pump includes a common-mode feedback loop to maintain the charging and discharging of the differential output nodes with respect to a common-mode voltage. Transconductance amplifiers are provided within the common-mode feedback loop to provide greater dynamic range to the charging and discharging of the differential output nodes.

Charge pump for a low-voltage wide-tuning range phase-locked loop

High speed CML logic gate systems for providing selected Boolean logic functions. Two halves of a substantially symmetric first system, having a relatively small number ( ) of CMOS transistors, are used to generate any of the logic functions AND, NAND, OR and NOR. Two halves of a substantially symmetric second system having another small number ( ) of transistors are used to generate any of the logic functions XOR, XNOR and NOT. In either system, the sum of currents passing through certain voltage-controlling gates is substantially constant.

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Xiang Zhu