United Microelectronics Corp.

Unisantis Electronics Singapore Pte. Ltd.

Agency for Science, Technology and Research

Certis Cisco Security Pte Ltd

Asm Technology Singapore Pte Ltd

Xiang Li

Yu-Cheng Tung

Navab Singh

Fujio Masuoka

Hiroki Nakamura

Ding-Lung Chen

Zhixian Chen

Shintaro Arai

Yisuo Li

Tomohiko Kudo

Vladimir Bliznetsov

Kavitha Devi Buddharaju

Nansheng Shen

Martin James Baptist

Keen Hon Wong

Honching Lui

King-Jien Chui

Yu Jiang

Poh Beng Tan

Shao-Hui Wu

Xinpeng Wang

En-Feng Liu

Hsiao Yu Chia

Ding Lung Chen

Nozomu Harada

Yam Mo Wong

Guo-Qiang Patrick Lo

Ka Shing Kwan

Tong Ming Liu

Aashit Ramachandra Kamath

Hing Leung Li

Zhong Ping Fang

Krishna Asundi Anand

Lin Seng Ong

Herawan Rinov

Zhongping Fang

Ivan Reading

Changda Yao

Liping Zhao

A method of manufacturing a capacitor structure is provided, including the following steps. A substrate is provided. A first doped silicon material layer is formed on the substrate. A surface flattening process is performed on the first doped silicon material layer through a plasma treatment. An insulating material layer is formed on the first doped silicon material layer after the surface flattening process is performed. A second doped silicon material layer is formed on the insulating material layer. The first doped silicon material layer is patterned into a first electrode. The insulating material layer is patterned into an insulating layer. The second doped silicon material layer is patterned into a second electrode. The method of manufacturing the capacitor structure may be used to produce a capacitor with better reliability and may improve capacitance density.

Method of manufacturing capacitor structure

A method for manufacturing semiconductor structure includes: providing a substrate having a first surface; forming a trench on the first surface, wherein a bottom surface and side walls of the substrate are configured along an outer periphery of the trench; annealing the substrate with high-purity argon or high-purity hydrogen to flatten the bottom surface and the side walls; conformally disposing a composite-material layer to cover the first surface, the bottom surface and the side walls; disposing a polysilicon material layer in the trench; removing the composite-material layer on the first surface; forming a multi-layer metal interconnection structure on the first surface and the polysilicon material layer, the multi-layer metal interconnection structure including a MEMS frame structure and through holes; removing the polysilicon material layer and the composite-material layer; using plasma treatment to the trench to flatten the bottom surface and the side walls. The plasma contains inert gas and hydrogen.

Method for manufacturing semiconductor structure and planarization process thereof

A semiconductor device includes a dielectric structure, a first source/drain electrode, a second source/drain electrode, an oxide semiconductor layer, a gate dielectric layer, and a first gate electrode. The first source/drain electrode is disposed in the dielectric structure. The oxide semiconductor layer is disposed on the first source/drain electrode in a vertical direction. The second source/drain electrode disposed on the oxide semiconductor layer in the vertical direction. The gate dielectric layer is disposed on the dielectric structure and surrounds the oxide semiconductor layer in a horizontal direction. The gate dielectric layer includes a first portion and a second portion. The first portion is elongated in the horizontal direction. The second portion is disposed on the first portion and elongated in the vertical direction. The first gate electrode is disposed on the first portion of the gate dielectric layer.

Semiconductor device and manufacturing method thereof

A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device includes a substrate, an interconnection structure, an oxide semiconductor (OS) transistor and a contact structure. The substrate has a first surface and a second surface opposite to the first surface. The interconnection structure is disposed on the first surface, and the oxide semiconductor (OS) transistor is disposed on the second surface. Also, the OS transistor includes a back gate disposed on the second surface of the substrate. The contact structure is formed between the OS transistor and the interconnection structure, and the contact structure is electrically connected to the back gate. The contact structure penetrates through the substrate for electrically connecting the interconnection structure to the OS transistor.

Semiconductor device and method of forming the same

A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.

Manufacturing method of oxide semiconductor device

A semiconductor device includes a substrate, a first transistor, a first diode structure, and a second diode structure. The first transistor is disposed on the substrate. The first transistor includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the substrate by the first diode structure. The first drain electrode is connected to the substrate by the second diode structure. The first diode structure and the second diode structure may be used to improve potential unbalance in the transistor, and operation performance and reliability of the semiconductor device may be enhanced accordingly.

Semiconductor device

A method of manufacturing an oxide semiconductor transistor is provided in the present invention, which includes the step of providing an oxide semiconductor transistor on the front side of a substrate, attaching a wafer on the front side of the substrate, forming a contact hole extending from the back side of the substrate to the oxide semiconductor layer of the oxide semiconductor transistor, and filling the contact hole with metal material to form a back gate of the oxide semiconductor transistor.

Oxide semiconductor transistor and method of manufacturing the same

The system provides secure controlled access to multiple Bluetooth devices issued to users. For example an officer may be issued a weapon. To enable monitoring of weapon status, a Bluetooth sensor may be fitted to a holster and the Officer issued with a Bluetooth enabled mobile phone. In order to establish a secure Bluetooth connection between the devices, sensor contains a restored link key and the mobile phone stores a partial link key. The supervisor enters their username and password, and a secret key into the phone which is then used with the partial link key to generate a copy of the link key stored in the first device, so that a secure connection can be established with the first device. The officer enters their username and password into the sensor, and once the secure connection is established it is sent over the secure connection to the mobile phone which then sends both user names and passwords to a verification authority. If the officer is verified and authorized to issue the devices, an authorization message is returned and use of the devices allowed. If the authorization fails, a failure message is returned and the devices are not issued and features may be blocked. The verification authority may be internal or external to the phone. If the authority is external, then the supervisor's user name and password could be omitted.

Bluetooth pairing system, method, and apparatus

A system for securely controlling access between two wireless (i.e. Bluetooth-enabled) apparatuses, also comprising a supervisor apparatus. The first apparatus is paired to the second by establishing a secure wireless (i.e. Bluetooth) link. The first apparatus includes a stored partial link key and a link key generator: The first apparatus receives a first secret key from the apparatus user, and may also receive a second secret key from the supervisor apparatus. The link key generator generates either a first link key based upon a stored first partial link key, the first secret key and the second secret key or a second link key based upon the stored first partial link key and the first secret key. An access control module in the second apparatus determines the level of access that the first apparatus is granted based upon the link key used to establish the secure connection&#x2014;full/restricted access.

Method and system for controlling access to wireless apparatuses

The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.

Surrounding gate transistor (SGT) structure

According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.

Resistive memory arrangement and a method of forming the same

Disclosed is an apparatus for mounting a transducer to a bond head of a wire bonder. In particular, the bond head of the wire bonder is operative to mechanically drive the transducer when forming electrical interconnections between separate locations within a semiconductor package. Specifically, the apparatus comprises: i) a flexural structure having a connector for connecting to the transducer, the flexural structure being configured to bend; and ii) at least one actuator attached to the flexural structure, the at least one actuator being operative to bend the flexural structure to thereby cause a displacement of the transducer connected thereto via the connector.

Wire bonder including a transducer, a bond head, and a mounting apparatus

A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.

Method for producing semiconductor device and semiconductor device

Growing community of inventors

Singapore, Singapore

Xiang Li