Yangtze Memory Technologies Co., Ltd.

Huazhong University of Science and Technology

Xiang Hui Zhao

Zui Xin Zeng

Baoyou Chen

Gang Yang

Lianjuan Ren

Jun Hu

Shi Zhang

Biao Zheng

Jian Dai

Hai Jin

Yu Zhang

Xiaofei Liao

Jin Zhao

Yicheng Chen

Beibei Si

A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.

Staircase formation in three-dimensional memory device

Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method for forming a hole structure having a first hole portion and a second hole portion connected to and over the first portion in a stack structure of a semiconductor device includes determining a hard mask layer. An etching resistivity of the hard mask layer may be inversely proportional to a difference between a first lateral dimension of the first hole portion and a second lateral dimension of the second hole portion, and the first lateral dimension may be less than the second lateral dimension. The method may also include forming the hard mask layer over the stack structure, and patterning the hard mask layer to form a first patterned hard mask layer that has a first mask opening. The first mask opening may have the first lateral dimension. The method may further include removing a portion of the stack structure exposed by the first patterned hard mask layer to form an initial hole structure in the stack structure, and patterning the first patterned hard mask layer to form a second patterned mask layer that has a second mask opening. The second mask opening may have the second lateral dimension. The method may further include removing another portion of the stack structure exposed by the second patterned hard mask layer to form the hole structure.

Methods for forming hole structure in semiconductor device

Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method includes forming a first etch mask over a stack structure, and removing a portion of the stack structure exposed by the first etch mask. The first etch mask may have a first mask opening with a first lateral dimension. The method may also include forming a second etch mask from the first etch mask. The second etch mask may have a second mask opening with a second lateral dimension that is greater than the first lateral dimension. The method may further include removing another portion of the stack structure exposed by the second etch mask to form the hole structure having a first hole portion and a second hole portion connected to and over the first hole portion.

The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.

FPGA-based dynamic graph processing method

Growing community of inventors

Hubei, China

Xiang Hui Zhao