Lumination LLC

Emcore Corporation

Gelcore, LLC

Iqe Rf, LLC

Iqe Plc

Velox Semiconductor Corporation

Xiang Gao

Michael Sackrison

LinLin Liu

Ivan Eliashevich

Hari S Venugopalan

Alex D Ceruzzi

Bryan S Shelton

Stephen Schwed

Milan Pophristic

Michael Murphy

Richard A Stall

Hugues Marchand

Mark Gottfried

Boris Peres

Oleg Laboutin

Chris Bohler

Shiping Guo

Steve Schwed

A passivated semiconductor device structure includes a III-nitride structure and a passivation layer. The III-nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.

Dielectric passivation for layered structures

A semiconductor structure includes a substrate and a semiconductor buffer structure overlying the substrate. The semiconductor buffer structure includes a semiconductor body of a gallium nitride material, and a stack of strain compensation layers. The stack of strain compensation layers includes a layer of a first semiconductor material with an in-plane lattice constant that is smaller than a lattice constant of the semiconductor body, and a layer of a second semiconductor material with an in-plane lattice constant that is greater than the lattice constant of the semiconductor body.

Semiconductor structure including buffer with strain compensation layers

Structures and fabrication processes are described for group III-nitride enhancement mode field effect devices in which a two-dimensional electron gas is present at or near the interface between a pair of active layers that include a group III-nitride barrier layer and a group III-nitride semiconductor layer. The barrier layer has a band gap wider than the band gap of the adjacent underlying semiconductor layer. The two-dimensional electron gas is induced by providing one or more layers disposed over the barrier layer. A gate electrode is in direct contact with the barrier layer. Ohmic contacts for source and drain electrodes are in direct contact either with the barrier layer or with a semiconductor nitride layer disposed over the barrier layer.

Group III-nitride enhancement mode field effect devices and fabrication methods

A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, and a first type window layer disposed over the intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer is disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.

PIN diode structure with zinc diffusion region

A light emitting chip is disposed on a support surface. A plurality of bonding bumps are disposed in a gap between the light emitting chip and the support surface. The plurality of bonding bumps provide at least one electrical power input path to the light emitting chip. An underfill comprising underfill material is disposed in the gap between the light emitting chip and the support surface such that the underfill substantially fills the gap but does not form a fillet extending outside the gap over sidewalls of the light emitting chip. The underfill is configured to provide at least one of (i) mechanical support for the light emitting chip and (ii) a thermal conduction path from the light emitting chip to the support surface.

Underfill for light emitting device

A surface mount LED package having a tight footprint and small vertical image size is fabricated by a method comprising: forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing; forming electrical vias in a sub mount, the electrical vias passing from a front side of the sub-mount to a back-side of the sub-mount; flip chip bonding the light emitting diode chips on the front-side of the sub mount such that each light emitting diode chip electrically contacts selected electrical vias; thinning or removing the substrates of the flip-chip bonded light emitting diode chips; and after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.

Wafer level package for very small footprint and low profile white LED devices

A light emitting device (A) includes a semiconductor die (). The semiconductor die includes: an epitaxial structure () arranged on a substrate (), the epitaxial structure forming an active light generating region () between a first layer () on a first side of the active region and having a first conductivity type, and a second layer () on a second side of the active region and having a second conductivity type, the second side of the active region being opposite the first side of the active region and the second conductivity type being different that the first conductivity type; a first contact () in operative electrical communication with the active region via the first layer in the epitaxial structure, the first contact being arranged on a side of the epitaxial structure opposite the substrate; a second contact () in operative electrical communication with the active region via the second layer in the epitaxial structure, the second contact being arranged on a side of the epitaxial structure opposite the substrate; a first contact trace corresponding to the first contact and defined at a surface thereof distal from the substrate, the first trace including at least one area designated for bonding (); and, a second contact trace corresponding the second contact and defined at a surface thereof distal from the substrate, the second trace including at least one area () designated for bonding. Suitably, the first contact trace is substantially enclosed within the second contact trace.

Optimized contact design for thermosonic bonding of flip-chip devices

A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, a first type window layer disposed over said intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.

A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.

PIN photodiode structure and fabrication process for reducing dielectric delamination

A light emitting semiconductor device die () includes an electrically insulating substrate (). First and second spatially separated electrodes () are disposed on the electrically insulating substrate. The first and second electrodes define an electrical current flow direction directed from the first electrode to the second electrode. A plurality of light emitting diode mesas () are disposed on the substrate between the first and second spatially separated electrodes. Electrical series interconnections () are disposed on the substrate between neighboring light emitting diode mesas. Each series interconnection carries electrical current flow between the neighboring mesas in the electrical current flow direction.

LED with series-connected monolithically integrated mesas

In a method for fabricating a flip-chip light emitting diode device, a submount wafer is populated with a plurality of the light emitting diode dies. Each device die is flip-chip bonded to the submount. Subsequent to the flip-chip bonding, a growth substrate is removed. The entire submount is immersed in the etchant solution, exposed to the light for a prespecified period of time, removed from the solution, dried and diced into a plurality of LEDs. The LEDs are immediately packaged without any further processing.

Increased light extraction from a nitride LED

In a light emitting package fabrication process, a plurality of light emitting chips () are attached on a sub-mount wafer (). The attached light emitting chips () are encapsulated. Fracture-initiating trenches () are laser cut into the sub-mount wafer () between the attached light emitting chips () using a laser. The sub-mount wafer () is fractured along the fracture initiating trenches ().

Laser separation of encapsulated submount

A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.

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Xiang Gao