Marvellworld Trade Ltd.

Marvell International Limited

National Semiconductor Corporation

Credo Technology Group Limited

Gyrfalcon Technology Inc.

Synopsys, Inc.

Kla Tencor Corporation

Marvell Asia Pte., Ltd.

Kla-tenor Corp.

Xiang Gao

Li Lin

Ali Djabbari

Gerard G Socci

Bram Nauta

Mounir Youssef Bohsali

Lin Yang

Leonid Poslavsky

Ahmad Reza Bahai

Qiang Zhao

Wanghua Wu

Wenhan Zhang

Eric Klumperink

Luns Tee

Chi-Hung Lin

Chih-Wei Yao

Torsten Rudolf Kaack

Philip D Flanner, Iii

Ming Di

Haoli Qian

Ali Kiaei

Arshan Aga

Cao-Thong Tu

Yi-Min Jiang

Olivier Burg

Chia-Chih Yen

Zhiming Jiang

Konstantinos Manetakis

Haisong Wang

Sashikala Venkata Obilisetty

Pedja Raspopovic

Eric A M Klumperink

Hsiang-Chieh Liao

Lixin Shao

Scott Penner

Mustafa Oguzhan Yayla

Ni Xu

Jun-Jie Ye

In one aspect, QoR metrics for different candidate macro placements are estimated using machine learning models. A set of candidate macro placements of hard macros within a circuit design is assessed by estimating a quality metric for each candidate macro placement, as follows. Model-specific estimates of the quality metric are predicted by applying different machine learning models to the candidate macro placements. The different machine learning models are trained using sets of completed macro placements for other circuit designs. The model-specific estimates of the quality metric are combined based on an applicability of (a) the set of macro placements used to train that model to (b) the set of candidate macro placements being evaluated.

Placing hard macros using machine learning predictions trained on different circuit designs

In some aspects, a graph is used to assist users in cause analysis of faults. The graph represents signal flow through a design of an integrated circuit The graph includes graph elements, such as nodes and edges. The nodes may represent cells and nets in the circuit design, and the edges may represent signal flow between the cells and nets. A propagation model for the propagation of faults through the graph is constructed. The propagation model includes local propagation models for the propagation of faults through the graph elements. Propagation of a known fault backward through the graph is modeled using the propagation model. This results in a causality ranking of the graph elements as possible causes of the known fault. Information indicative of the causality ranking is displayed in a user interface that shows the design of the integrated circuit.

In-graph causality ranking for faults in the design of integrated circuits

Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

Systems and methods for phase synchronization of local oscillator paths in oscillator-operated circuits

An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.

PLL with wide frequency coverage

Integrated circuits such as multi-channel transceivers may share oscillators having loop inductors. To minimize the driving distance from the shared oscillators to the transceiver modules, the loop inductor may be equipped with an additional sense port diametrically opposite to the drive port. An oscillator drive core may be coupled to the drive port to provide an oscillating signal at the drive and sense ports. The oscillating signals can be converted into digital clock signals by way of a differential amplifier. Three-loop inductor designs and/or multi-winding inductor designs may be preferred for minimizing parasitic effects of the added sense port.

Multiport inductors for enhanced signal distribution

Embodiments described herein provide circuitry employing an inductor having enhanced circuit area usage. The circuitry includes an inductor having a first loop and a second loop adjoining the first loop to form a figure-eight configuration. The circuitry further includes a circuit component disposed at least partially inside an area defined by at least one of the first loop and the second loop. The inductor has an intersection portion between the first loop and the second loop. An input node is located proximate to the intersection portion, the input node having a first extension disposed inside the first loop. An output node is located proximate to the intersection portion. The output node has a second extension disposed inside the second loop. At least a first capacitor is coupled to the input node and the second extension, and at least a second capacitor coupled to the output node and the first extension.

Systems and methods for an inductor structure with enhanced area usage of a circuit

Methods of encoding image data for loading into an artificial intelligence (AI) integrated circuit are provided. The AI integrated circuit may have an embedded cellular neural network for implementing AI tasks based on the loaded image data. An encoding method may apply image splitting, principal component analysis (PCA) or a combination thereof to an input image to generate a plurality of output images. Each output image has a size smaller than the size of the input image. The method may load the output images into the AI chip, execute programming instructions contained in the AI chip to generate an image recognition result based on the at least one of the plurality of output images, and output the image recognition result. The encoding method also trains a convolution neural network (CNN) and loads the weights of the CNN into the AI integrated circuit for implementing the AI tasks.

System and method for encoding data in an image/video recognition integrated circuit solution

Methods of encoding voice data for loading into an artificial intelligence (AI) integrated circuit are provided. The AI integrated circuit may have an embedded cellular neural network for implementing AI tasks based on the loaded voice data. An encoding method may generate a two-dimensional (2D) frequency-time array from an audio waveform, use the 2D frequency-time array to generate a set of 2D arrays to approximate the 2D frequency-time array, load the set of 2D arrays into the AI integrated circuit, execute programming instructions contained in the AI integrated circuit to feed the set of 2D arrays into the embedded cellular neural network in the AI integrated circuit to generate a voice recognition result, and output the voice recognition result. The encoding method also trains a convolution neural network (CNN) and loads the weights of the CNN into the AI integrated circuit for implementing the AI tasks.

System and method for encoding data in a voice recognition integrated circuit solution

An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop, a phase interpolator, a sampling element, a phase detector, a phase control filter, and a frequency control filter. The phase interpolator applies a controllable phase shift to the clock signal from the frac-N PLL to provide a sampling signal to the sampling element. The phase detector estimates timing error of the sampling signal relative to the analog receive signal. The phase control filter derives a phase control signal for the phase interpolator which operates to minimize a phase component of the estimated timing error. The frequency control filter derives the frequency control signal in a fashion that separately minimizes a frequency offset component of the estimated timing error, reducing the interpolator's phase rotation rate.

Fractional-N PLL based clock recovery for SerDes

Methods of encoding voice data for loading into an artificial intelligence (AI) integrated circuit are provided. The AI integrated circuit may have an embedded cellular neural network for implementing AI tasks based on the loaded voice data. An encoding method may generate a two-dimensional (2D) frequency-time array from an audio waveform, apply a probability function to the 2D frequency-time array to generate a set of 2D arrays, load the set of 2D arrays into the AI integrated circuit, execute programming instructions contained in the AI integrated circuit to feed the set of 2D arrays into the embedded cellular neural network in the AI integrated circuit to generate a voice recognition result, and output the voice recognition result. The encoding method also trains a convolution neural network (CNN) and loads the weights of the CNN into the AI integrated circuit for implementing the AI tasks.

Embodiments described herein provide a method for correcting a propagation delay induced error in an output of an asynchronous counter. An input clock is applied to the asynchronous counter. A gray-code count is generated by the asynchronous counter. The gray-code count is mapped to a binary count. An error component, indicative of a counting error induced by a propagation delay between the input clock and the binary count, is generated by taking an exclusive-OR operation over the gray-code count and the input clock. The error component is added to the binary count to generate an error-corrected binary count. The error-corrected binary count is output.

Systems and methods for gray coding based error correction in an asynchronous counter

Methods and systems of process control and yield management for semiconductor device manufacturing based on predictions of final device performance are presented herein. Estimated device performance metric values are calculated based on one or more device performance models that link parameter values capable of measurement during process to final device performance metrics. In some examples, an estimated value of a device performance metric is based on at least one structural characteristic and at least one band structure characteristic of an unfinished, multi-layer wafer. In some examples, a prediction of whether a device under process will fail a final device performance test is based on the difference between an estimated value of a final device performance metric and a specified value. In some examples, an adjustment in one or more subsequent process steps is determined based at least in part on the difference.

Calculated electrical performance metrics for process monitoring and yield management

A system includes a signal generator and a signal combiner. The signal generator is configured to output a first signal having a first frequency and to output one or more signals having the first frequency and having phases shifted relative to the first signal by predetermined amounts. The signal combiner is configured to combine the first signal and the one or more signals to output a frequency multiplied second signal having a second frequency. The second frequency is greater than the first frequency.

Frequency multipliers

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Xiang Gao