Yangtze Memory Technologies Co., Ltd.

Xiang Fu

Qiang Tang

Qi Wang

Zilong Chen

Zhiliang Xia

Huangpeng Zhang

Shiyang Yang

Huang Peng Zhang

Zhi Chao Du

Yan Lu

Xin Yun Huang

Hua Min Cao

Chunfei Deng

Ling Ding

Wen Wen Dong

Shu Bing Xu

Methods for input/output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.

Input/output reference voltage training method in three-dimensional memory devices

A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (V) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (V) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (V) on an unselected word line (Unsel_WL).

Method for reading three-dimensional flash memory

A memory device includes a string of cells having one and more top selection cells, one or more dummy memory cells, and memory cells, and a peripheral circuit coupled to the string of cells. The peripheral circuit is configured to verify a threshold voltage of at least one of the one or more top selection cells or the one or more dummy memory cells to determine whether the at least one of the one or more top selection cells or the one or more dummy memory cells has failed. In response to the at least one of the one or more top selection cells or the one or more dummy memory cells being failed, the peripheral circuit is further configured to reset the at least one of the one or more top selection cells or the one or more dummy memory cells.

Memory device capable of reducing program disturbance and erasing method thereof

A controller includes memory and a microcontroller coupled to the memory. The memory is configured to store a list of entries of data in Flash memory coupled to the controller. The microcontroller is configured to periodically update the list of entries based on data programmed into the Flash memory, and check the list of entries upon reading data from the Flash memory.

Electronic apparatus and method of managing read levels of flash memory

An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.

An electronic apparatus including flash memory and a flash controller is provided. The flash controller is coupled to the flash memory and used to manage data access to the flash memory. The flash controller includes a timer, memory and a microcontroller coupled to the timer and the memory. The timer is used to generate clock interrupts. The memory is used to retain for a predetermined period of time a list of entries of data programmed into the flash memory. Upon each clock interrupt, the microcontroller is used to write an entry of data being programmed into the flash memory to update the list of entries.

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.

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Wuhan, China

Xiang Fu