Intel Corporation

Xiang Chris Zou

Hong Wang

Gautham N Chinya

Bryant E Bigbee

Shivnandan D Kaushik

Per H Hammarlund

John Thomas Shen

Baiju V Patel

Prashant Sethi

Richard A Hankins

Scott Dion Rodgers

Xinmin Tian

Anil Aggarwal

John P Shen

Perry H Wang

Robert Geva

John L Reid

Robert P Knight

Jason W Brandt

James Paul Held

Chris J Newburn

Milind Baburao Girkar

Ittai Anati

Dion Rodgers

Piyush N Desai

Gilbert A Neiger

Andrew V Anderson

Richard A Uhlig

Stalinselvaraj Jeyasingh

Steven M Bennett

Alain Kagi

Trung Am Diep

Sanjiv M Shah

Ryan N Rakvic

Justin Hogaboam

Shavindra Premaratne

Edward Thomas Grochowski

Quinn Able Jacobson

Lawrence O Smith

Paul M Petersen

Anne Y Matsuura

Sonika Johri

Ed Grochowski

Anil Aggawal

Carlos V Rozas

Ron Gabor

James B Crossland

Joseph Nuzman

Darrell D Boggs

Igor Yanover

Alaa R Alameldeen

Douglas M Carmean

Abhishek Basak

Doron Orenstein

Michael A Kozuch

Rajesh S Parthasarathy

Debabrata Mohapatra

James Charles Abel

Francis McKeen

Deepak A Mathaikutty

Larry O Smith

David K Poulsen

Madhavan Parthasarathy

Alain Kägi

Shiv Kaushik

Sang Kyun Kim

Fangfei Liu

Steve M Bennett

Lawrence Smith, Iii

Adam Holmes

Sahar Daraeizadeh

Jim B Crossland

Xin-chuan Wu

Pradnya Laxman Khalate

Shivanandan Kaushik

Apparatus and method for compiling and executing hybrid classical-quantum programs. For example, one embodiment of a method comprises: reading source code specifying both non-quantum operations to be performed by a host processor and quantum operations to be performed by a quantum accelerator; compiling the source code to generate a target object file, wherein portions of the source code specifying the quantum operations are compiled into quantum basic blocks (QBBs) in the target object file, each QBB comprising one or more quantum instructions to be executed by the quantum accelerator and wherein portions of the source code specifying the non-quantum operations are compiled into native instructions to be executed by the host processor.

Hybrid compilation apparatus and method for quantum-classical code sequences

Apparatus and method for scalable representations of arbitrary quantum computing rotations. For example, one embodiment of an apparatus comprises: a memory to store a first waveform; and a base envelope generator to implement a base envelope, the base envelope applied to the first waveform to generate a second waveform usable to cause quantum rotation of a specified angle on a target quantum bit (qubit) of a quantum processor, and wherein the base envelope is selected out of a first plurality of envelopes based one or more characteristics specific to the target qubit on which the quantum rotation is performed.

Apparatus and method including scalable representations of arbitrary quantum computing rotations

An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.

Apparatus and method for scalable qubit addressing

Apparatus and method for specifying quantum operation parallelism. For example, one embodiment of an apparatus comprises: instruction fetch circuitry to fetch a plurality of quantum instructions from a memory or a cache; slice-based instruction processing circuitry to identify quantum circuit slices comprising sets of one or more of the plurality of quantum instructions; and one or more instruction decoders to decode the quantum instructions to generate quantum microoperations; and quantum execution circuitry to execute sets of the quantum microoperations in parallel based on the quantum circuit slices.

Apparatus and method for specifying quantum operation parallelism for a quantum control processor

Apparatus and method for injected spin echo sequences in a quantum processor. For example, one embodiment of a processor includes a decoder to decode quantum instructions to generate quantum microoperations (uops) and to decode non-quantum instructions to generate non-quantum uops, execution circuitry to execute the quantum uops and non-quantum uops, and a corrective sequence data structure to identify and/or store corrective sets of uops for one or more of the quantum instructions. The decoder is to query the corrective sequence data structure upon receiving a first quantum instruction to determine if one or more corrective uops exist, and if the one or more corrective uops exist, the decoder is to submit the one or more corrective uops for execution by the execution circuitry.

Apparatus and method for injecting spin echo micro-operations in a quantum processor

Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

Restricted speculative execution mode to prevent observable side effects

Apparatus and method for performing a quantum rotation operation. For example, one embodiment of an apparatus comprises: a decoder to decode a plurality of instructions; execution circuitry to execute a first instruction or first set of the instructions to generate a floating point (FP) value and to store the FP value in a first register; the execution circuitry to execute a second instruction or second set of the one or more of the instructions to read the FP value from the first register and compress the FP value to generate a compressed FP value having a precision selected for performing quantum rotation operations; and quantum interface circuitry to process the compressed FP value to cause a quantum rotation to be performed on one or more qubits of a quantum processor.

Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.

Apparatus and method for quantum performance and/or error correction enhancement using multi-qubit gates

A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.

Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuits

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Programmable event driven yield mechanism which may activate other threads

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Systems, Methods and apparatuses relating to processor cores that respond to interrupts are disclosed. In one embodiment, an apparatus includes an interrupt interface, a memory interface; and a processor core to generate an interrupt acknowledge signal in response to a received interrupt; receive data in return; determine whether the received data is an interrupt service routine address, the interrupt service routine address being stored in an interrupt vector translation lookaside buffer; and, if not, use the received data to calculate the interrupt service routine address; wherein the processor core is further to use the interrupt service routine address to issue a request on the memory interface to fetch the interrupt service routine, and to execute the interrupt service routine.

Interrupt-vector translation lookaside buffer

Growing community of inventors

Beaverton, OR, United States of America

Xiang Chris Zou