United Microelectronics Corp.

Xian Feng Du

Guohai Zhang

Guoan Du

Yuan Zhou

Han Wang

A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

Semiconductor memory device and fabrication method thereof

A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the substrate, a control gate formed on the blocking dielectric layer, and a tri-layered charge-trapping layer sandwiched between the tunnel dielectric layer and the blocking dielectric layer. Furthermore, the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer. The bottom nitride layer includes a first nitride concentration, the top nitride layer includes a second nitride concentration, and the middle nitride layer includes a third nitride concentration. And the third nitride concentration is larger than the first nitride concentration and the second nitride concentration.

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Xian Feng Du