Altera Corporation

Xiabao Wang

Chiakang Sung

Khai Nguyen

Joseph Huang

Bonnie I Wang

Yan Chong

Philip Pan

In Whan Kim

Boon Jin Ang

Tzung-Chin Chang

Gopinath Rangan

Ket Chiew Sia

Jonathan Chung

Foong Tek Chan

A high speed IO buffer is disclosed. The high speed IO buffer includes a first P-type metal oxide semiconductor (PMOS) transistor coupled to an IO voltage source. The high speed IO buffer also includes a first N-type metal oxide semiconductor (NMOS) transistor coupled to a ground source, a second PMOS transistor coupled to the first PMOS transistor and a pad and a second NMOS transistor coupled to the first NMOS transistor and the pad. The first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor are arranged in a cascoded arrangement.

High speed IO buffer

An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Input buffer for multiple differential I/O standards

Growing community of inventors

Cupertino, CA, United States of America

Xiabao Wang