Intel Corporation

Other

Xia Dai

Keng L Wong

John T Orton

Leslie E Cline

Edwin J Pole, Ii

Millind Mittal

Thomas D Fletcher

Gurbir Singh

John William Horigan

Greg F Taylor

Hung-Piao Ma

Borys S Senyk

Cau L Nguyen

Varghese George

Stephen H Gunther

Robert J Greiner

Gregory F Taylor

Krishnan Ravichandran

Terry I Chappell

Robert L Farrell

George L Geannopoulos

Raviprakash Nagaraj

Ravi Nagaraj

Kent R Callahan

Douglas R Parker

Ravishankar Kuppuswamy

Scott R Rushford

George Geannopuolos

Eric S Swartzendruber

The present invention relates to a secured transaction system. In one embodiment, a mobile transaction processing agent system includes a communication module configured to receive a secured transaction description from a mobile client device or an encrypted transaction description from a point-of-sale (POS) device, wherein the secured transaction description is in the form of a bar code generated by the mobile client device, an authentication module configured to decode the secured transaction description and verify the secured transaction description is valid based on the mobile client device or the point-of-sale device, and a transaction processing module configured to process the transaction in accordance with the secured transaction description.

Secured transaction system

The present invention relates to a secured transaction system. In one embodiment, a point-of-sale (POS) system includes an input module configured to receive a transaction description from a mobile client device, an encryption engine configured to generate an encrypted transaction description using the transaction description from the mobile client device, and a communication module configured to transmit the encrypted transaction description for processing.

Secured point-of-sale transaction system

The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Dynamic voltage transitions

In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

Method and apparatus for enabling a low power mode for a processor

A method and an apparatus to dynamically transition a processor between two performance states, high performance and low power. Predetermined core clock frequency and supply voltage levels of the processor define each performance state. Transitioning the supply voltage while the processor is in the active mode and transitioning the frequency while the processor is in the sleep mode significantly reduce the processor latency.

Method and apparatus to enhance processor power management

A selectable control over multiple clock frequency/voltage level combinations that can be activated in a processor. A table can be placed in hardware that defines multiple combinations of CPU clock frequency and CPU operating voltage. By placing the table in hardware, it can be assured that all the various combinations will work for the particular processor device. Software can then be used to select a combination from this table, to control the actual frequency/voltage combination that is being implemented at a given time. This allows dynamic control over the power/performance tradeoff, so that the system can see maximum power savings consistent with acceptable performance, as operating and environmental considerations continue to change the most desirable selections.

System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field

In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicate the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

A computer display screen that functions as an information processing device such as a PALM, PIN or PDA when detached from the computer is disclosed.

Dual function electronic display screen

In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The voltage from a first voltage regulator supplied to a core of the processor may be lowered to a level at which the processor core becomes non-operational and the processor state is lost. The processor may include a memory region in which the processor state may be stored upon entering the low power state. This memory region may be powered by a second voltage regulator so that its contents are not lost while in the low power state. For one embodiment of the present invention, the processor may additionally include a snoop controller powered by the second voltage regulator. This snoop controller may snoop a cache, which may also be powered by the second voltage regulator, while the processor is in the low power state. The snoop controller may additionally monitor interrupts.

Method and apparatus for enabling a self suspend mode for a processor

A method and apparatus for reducing a microprocessor's power dissipation. In one embodiment a microprocessor includes a clock circuit, a core coupled to said clock circuit, and an on-die logic circuit coupled to said clock circuit to operate independent of a connection for power to said core, the on-die logic circuit includes a snoop request monitor coupled to a bus, and a snooping memory circuit.

Method, apparatus, and system to reduce microprocessor power dissipation

The present invention allows enhancement of a microprocessor's performance. Microprocessor-operated devices are designed for worst-case operating conditions, a thermal design power limit, such as software application instruction mix, and ambient temperature around the microprocessor. Designing for these worst-case conditions reduces the capabilities of microprocessors that do not continuously operate under worst-case operating conditions. The present invention comprises a method, apparatus, and machine-readable medium to increase a microprocessor's speed by facilitating operation of the microprocessor above the thermal design power limit.

Method, apparatus, and machine-readable medium to enhance microprocessor performance

Leakage power consumption may be reduced in computers and other devices by providing a state where clocks are off and a low supply voltage is provided to the processor. This voltage may be sufficiently low to prevent adverse consequences while dramatically reducing leakage current. In addition, caches may be flushed to reduce the soft error rate.

Reducing sleep mode subthreshold leakage in a battery powered device by making low supply voltage less than twice the threshold voltage of one device transistor

An apparatus is described for detecting presence of a user. The apparatus includes at least one thermal sensor to sense temperature around a define area of a computer system and a user presence detection subsystem coupled to the thermal sensor. The user presence detection subsystem determines presence of a user by analyzing signals output by the thermal sensor during a sampling period.

Computer screen power management through detection of user presence

One embodiment of the present invention, an eight bit binary adder with a typical latency independent of its width, is described. The adder comprises a four bit adder for calculating bits S -S of the sum, plus four bitslice circuits, one for speculatively calculating each of bits S -S of the sum. The calculation of the carry bit out of each bitslice is limited to the operands bits into that bitslice and the three preceding bitslices. Each bitslice also includes circuitry for detecting a potential error in the speculative sum such that the speculative sum can be corrected when there is a potential error.

Method and apparatus for speculative addition using a limited carry

A method and apparatus for generating multiple locked self-timed pulsed clock signals is disclosed. Race margins are reduced over separate clock generating circuits by sharing the necessary delay circuit elements between the multiple clock generating circuits. An edge is gated with a delayed edge to form the first clock pulse. A subsequent second clock pulse is generated by gating a partially-delayed edge with the first clock pulse, which minimizes race margins and pulse evaporation.

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San Jose, CA, United States of America

Xia Dai