Fudan University

Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Suzhou Oriental Semiconductor Co., Ltd.

Xi Lin

Pengfei Wang

Wei Zhang

Yi Hua Shen

Qingqing Sun

Wei Wang

Yu Wang

Jian Pan

Xiaoyong Liu

Wei Liu

Lei Liu

Yi Gong

Sheng Wang

Sen Sheng Li

A method for forming a semiconductor structure includes providing a substrate, forming a stop layer over a surface of the substrate, forming a dielectric layer over a surface of the stop layer, forming a first opening in the dielectric layer and exposing a portion of the stop layer, modifying the portion of the stop layer exposed at a bottom of the first opening to form a modification layer, and removing the modification layer to form a second opening from the first opening.

Semiconductor structure and method for forming the same

A field-effect-transistor includes forming a fin structure on a substrate, a gate structure formed across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.

Field-effect-transistors

A self-heating effect apparatus includes a memory and a processor. The processor is coupled to the memory and configured to process a self-heating effect model for characterizing a heat flow network of devices. The devices include a device under test and one or more adjacent devices surrounding the device under test. The self-heating effect model includes a reference thermal resistance and a reference thermal capacity; a thermal temperature feedback model used to acquire a thermal level of the device under test; a thermal resistance modification model used to acquire a modified thermal resistance of the device under test according to the thermal level of the device under test and the reference thermal resistance; and a thermal capacity modification model used to acquire a modified thermal capacity of the device under test according to the thermal level of the device under test and the reference thermal capacity.

Self-heating effect apparatus and test method

A dynamic random access memory (DRAM) is provided and includes a base substrate. The base substrate includes a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and covering portions of side surfaces of the plurality of fins. The dynamic random access memory further includes an interlayer dielectric layer formed over the base substrate and covering top surfaces of the plurality of fins and the isolation structure; and a memory structure, formed in an opening passing through the interlayer dielectric layer and each of the plurality of fins, the opening extending to and exposing a top surface of a portion of the isolation structure. The memory structure includes a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer.

Dynamic random access memory

Dynamic random access memory (DRAM) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming doped source/drain regions in the base substrate at two sides of the gate structure, respectively; forming an interlayer dielectric layer over the gate structure, the base substrate and the doped source/drain regions; forming a first opening, exposing one of the doped source/drain regions at one side of the gate structure, in the interlayer dielectric layer; and forming a memory structure in the first opening and on the one of doped source/drain regions.

Dynamic random access memory and fabrication method thereof

Dynamic random access memory (DRAM) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming an interlayer dielectric layer over the base substrate; forming an opening passing through the interlayer dielectric layer; and forming a memory structure, having a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer, in the opening.

A method for fabrication a field-effect-transistor includes forming a plurality of fin structures on a substrate, forming a gate structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, forming a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and forming a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.

Field-effect-transistors and fabrication methods thereof

The present invention discloses a power Metal Oxide Semiconductor (MOS) transistor, wherein a second U-shaped trench is formed below a first U-shaped trench, so that a field oxidation stress transition region can be extended, so as to greatly reduce current leakage caused by the field oxidation stress and improve the reliability of the device; and a charge compensation region is provided in a drift region at the bottom of the second U-shaped trench, and a super-junction structure is formed between the charge compensation region and the drift region to improve the breakdown voltage of the power device. According to the present invention, the second U-shaped trench and the charge compensation region are formed by a self-aligning process, so that the technical process is simple, reliable and easy to control, and can reduce the manufacturing cost of the power MOS transistor and improve its yield.

Power MOS transistor and manufacturing method therefor

The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor forms a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient.

Metal-oxide-semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM) and the manufacturing methods thereof

The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient.

Tunnel transistor structure integrated with a resistance random access memory (RRAM) and a manufacturing method thereof

The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors.

Photo detector consisting of tunneling field-effect transistors and the manufacturing method thereof

The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor faults a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient.

The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree.

Method for manufacturing a tunneling field effect transistor with a U-shaped channel

The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost.

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Shanghai, China

Xi Lin