International Business Machines Corporation

Xi Li

Kangguo Cheng

Richard Stephan Wise

Johnathan E Faltermeier

Geng Wang

Chengwen Pei

Viorel C Ontalus

Patrick Joseph O'Sullivan

Renee Tong Mo

Anil Kumar Chinthakindi

Deok-Kee Kim

Habib Hichri

Richard Stephen Wise

Rashmi Jha

James C Thorburn

Jesus Alberto Omana Iglesias

Huilong Zhu

Vijay Narayanan

Sivananda K Kanakasabapathy

Ying Di Zhang

Ravikumar Ramachandran

Babar Ali Khan

Eduard Albert Cartier

Siddarth A Krishnan

Vamsi Krishna Paruchuri

Wesley Charles Natzle

Kathryn Turner Schonenberg

David M Dobuzinsky

Naim Moumen

Kevin R Winstel

Ricardo Alves Donaton

Ming Cai

Joyce C Liu

Jinghong Li

Michelle Leigh Steen

Russell Herbert Arndt

Thomas A Wallner

Richard O Henry

Scott D Allen

Mark Todhunter Robson

Frank D Tamweber, Jr

An approach is provided to analyze data center performance. The approach includes analyzing the data centers, with each of the data centers are represented by a plurality of data center records. Available capacity at each of the data centers is identified based on the selected data center's set of data center records. In addition, a current workload currently being performed by each of the data centers is identified. The approach compares the identified current workload of each data center with the identified available capacity at the other data centers. Data centers are added to a consolidation consideration list in response to the comparisons. The consolidation consideration list is further analyzed to select data centers for consolidation or elimination.

Cohort cost analysis and workload migration

An approach is provided to visually depict cohort data to a user. The approach includes receiving a cohort display request (e.g., from a user, etc.). In response to the request, the approach retrieves a plurality of cohort data records, with each of the cohort data records corresponding to a cohort selected from a group of cohorts. In this approach, the group of cohorts represent similar computer systems. The approach displays a set of graphic user interface (GUI) controls on a display device, with each of the GUI controls corresponds to one of the retrieved cohort data records. A user selection is received that corresponds to a selected one of the GUI controls. The system responds by executing a cohort action on the cohort corresponding to the selected GUI control.

Cohort manipulation and optimization

A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.

Trench capacitor with spacer-less fabrication process

A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Semiconductor structures and methods of manufacturing the same

Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.

Method for simultaneously forming features of different depths in a semiconductor substrate

A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.

Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers

A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subjected to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and a horizontal fill portion of the spacer layer remains in one more recesses present in the STI regions so as to substantially planarize the STI region prior to subsequent material deposition thereon.

Shallow trench isolation recess repair using spacer formation process

A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.

Trench capacitor

In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.

Bottle-shaped trench capacitor with enhanced capacitance

A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided. The device structure includes a semiconductor substrate having a deep trench therein; and a first conductive layer and a second conductive layer sequentially disposed on said deep trench, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate.

Method and structure for forming trench DRAM with asymmetric strap

The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Dielectric spacer removal

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Somers, NY, United States of America

Xi Li