Nvidia Corporation

Xi He

Jianjun Chen

Wei Feng

Dong Zhang

Sangeun Han

Ranga Ramanujam Srinivasan

Yongmao Tang

Chunfeng Yang

Zejun Hu

Hank Fan

Xinyang Yu

Disclosed are apparatuses, systems, and techniques that may perform methods of pyramid optical flow processing with efficient identification and handling of object boundary pixels. In pyramid optical flow, motion vectors for pixels of image layers having a coarse resolution may be used as hints for identification of motion vectors for pixels of image layers having a higher resolution. Pixels that are located near apparent boundaries between foreground and background objects may receive multiple hints from lower-resolution image layers, for more accurate identification of matching pixels across different image levels of the pyramid.

Optical flow techniques and systems for accurate identification and tracking of moving objects

Disclosed are techniques for compressing data of an image using multiple processing cores. The techniques include obtaining, using a first (second, etc.) processing core, a first (second, etc.) plurality of reconstructed blocks approximating source pixels of a first (second, etc.) portion of an image and filtering, using the first processing core, the first plurality of reconstructed blocks. The filtering includes enabling application of one or more filters to a first plurality of regions that include pixels of the first plurality of reconstructed blocks but not pixels of the second plurality of reconstructed blocks. The filtering further includes disabling application of the one or more filters to a second plurality of regions that include pixels of the first plurality of reconstructed blocks and pixels of the second plurality of reconstructed blocks.

Parallel encoding of video frames without filtering dependency

Disclosed are apparatuses, systems, and techniques for real-time codec encoding of video files using hardware-assisted accelerators that utilize a combination of parallel and sequential processing, in which at least a part of intra-frame block prediction is performed with parallel processing.

Hardware codec accelerators for high-performance video encoding

Disclosed are techniques for compressing data of an image. Intermediate pixels may be determined. Each location of the image may be associated with a block of a plurality of blocks of a first size and a block of a plurality of blocks of a second size. For each block of the first size and of the second size, a first cost for a first mode and a second cost for a second mode may be determined in parallel using the intermediate pixels. A final mode and a final block size may be selected for each location of the image using the first cost and the second cost for each of a respective block of the first size and a respective block of the second size associated with a corresponding location. Final pixels may be determined, and a representation of the image may be obtained based on the final pixels.

Parallel processing of video frames during video encoding

A method for using an average motion vector in a motion vector search process. The method includes accessing an input frame for processing and reading average motion vector information from memory. The method further includes performing a motion vector search by using the average motion vector and a plurality of hints, calculating a winner motion vector based on the average motion vector and the plurality of hints, and storing the winner motion vector back into memory to create a new updated average motion vector. The method further includes finishing processing the input frame using the winning motion vector.

Using an average motion vector for a motion search

The present disclosure discloses a video encoder, a video encoding system and a video encoding method. The video encoder comprises a logic control module and an encoding module. Wherein, the logic control module is configured to receive a control command sent from an external controller for encoding a specified portion of each frame of image, and send the control command to the encoding module; and the encoding module is configured to receive the control command from the logic control module, and encode the specified portion of each frame of image according to the control command, so as to cooperate with a plurality of other video encoders to complete encoding each frame of image. By employing the video encoder, video encoding system and video encoding method according to the present disclosure, each frame of image can be accomplished jointly by a plurality of video encoders, thus significantly reducing the encoding time, diminishing the encoding latency, and achieving real-time encoding of high-definition video sources, in particular, video sources with a resolution ratio of 4 k or above.

Growing community of inventors

Shanghai, China

Xi He