Intel Corporation

Xavier Vera

Javier Carretero Casado

Jaume Abella

Tanausu Ramirez

Antonio Gonzalez

Antonio González

Pedro Chaparro Monferrer

Osman Unsal

Oguz Ergin

Enric Herrero Abellanas

Matteo Monchiero

Nicholas Axelos

Vivek K De

Ming Lei Zhang

Muhammad M Khellah

Christopher B Wilkerson

Enric Herrero

Daniel Sanchez

Jose-Alejandro Pineiro

Ronny Ronen

Javier C Casado

Enric H Abellanas

Daniel Sanchez Pedreño

Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Disabling cache portions during low voltage operations

An apparatus for storing X-bit digitized data, the register file comprising: a plurality of registers each register configured for storing X bits, wherein each register is partitioned into Y sub-registers such that each sub-register stores at least X/Y bits, and wherein at least one extra X/Y-bit sub-register is incorporated in each register to provide redundancy in the number of sub-registers for a total of at least Y+1 sub-registers per register, so that if a first sub-register in a first register includes faulty bits, data destined for storage in the first sub-register is stored in a second sub-register, in the first register, that does not include faulty bits.

Capacity register file

A method of an aspect includes determining a different operational configuration for each of a plurality of different maximum failure rates. Each of the different maximum failure rates corresponds to a different task of a plurality of tasks. The method also includes enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration. Other methods, apparatus, and systems are also disclosed.

Enforcing different operational configurations for different tasks for failure rate based control of processors

An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.

Traffic control on an on-chip network

Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.

Register error protection through binary translation

Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.

Fault-aware mapping for shared last level cache (LLC)

A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.

Increased error correction for cache memories through adaptive replacement policies

Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.

Recovering from data errors using implicit redundancy

Embodiments of systems, apparatuses, and methods for reducing data cache power consumption and error protection overhead are described. In some embodiments, the data cache is partitioned into cache portions. Each cache portion stores data that has a different fault tolerance and uses a different type of error detection mechanism than the other cache portions.

Content-aware caches for reliability

A method of determining vulnerability of a cache memory includes associating a first counter with a cache element and periodically incrementing the first counter. When a read or other access that consumes the data in the cache element occurs, a current value of the first counter is accumulated. When a write or other cache access that modifies data in the cache element occurs, the first counter is reset. At the end of an evaluation period, the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable. Dividing this value by the number of clock cycles approximates the vulnerability of this cache element. The vulnerability for a subset of all cache elements may be measured and extrapolated to obtain an estimate for the vulnerability of the cache memory as a whole.

Vulnerability estimation for cache memory

Embodiments of apparatuses, methods, and storage medium associated with selectively providing error correction to memory are disclosed herein. In one instance, an apparatus may include a memory controller configured to control access to a non-volatile memory having storage locations. The controller may be configured to provide a first error correction arrangement to provide a first level of error correction capability for data stored in the non-volatile memory. The memory controller may include a control/error correction block configured to provide a second error correction arrangement with a second level of error correction capability for data stored in the non-volatile memory. The second level of error correction capability enables correction of at least one bit error more than the first level. The memory controller may be configured to selectively employ the second error correction arrangement to complement the first error correction arrangement. Other embodiments may be described and claimed.

Selective provision of error correction for memory

In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed.

Banking of reliability metrics

Methods and apparatus to reduce aging effect on registers are described. In one embodiment, a select value is stored in a register that is unused, for example, to reduce the effects of negative bias temperature instability (NBTI) or oxide degradation on the register. Other embodiments are also described.

Reducing aging effect on registers

Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.

Growing community of inventors

Barcelona, Spain

Xavier Vera