Synopsys, Inc.

Xavier Guerin

Alexander Rabinovitch

A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal. The method further includes transforming the first data into a second data representative of a second design. The second data includes a third data associated with a second sequential element including functionality of the first sequential element and a fourth data associated with a first logic circuit. The evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i&#x2212;1 of the hardware verification system when the second data is compiled for programming into the hardware verification system, where i is an integer number.

Overlaying of clock and data propagation in emulation

A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving, in the computer, a first code representing a first design including a first latch configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system. The method further includes changing, using the computer, the first code into a second code representing a second design, the changing further including transforming, using the computer, the first latch into a second latch configured to be evaluated in accordance with a second signal different from the first signal after the first signal is received at the second latch, when the second code for the second design is compiled for programming into the hardware verification system.

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Wissous, France

Xavier Guerin