Intel Corporation

Tokyo Electron Limited

Xavier Francois Brun

Sanka Ganesan

Chandra Mohan Jha

Osamu Hirakawa

Jason M Gamba

Charles Wayne Singleton, Jr

Robert Alan May

Pooya Tadayon

Ram S Viswanath

Tarek A Ibrahim

Manish Dubey

Weihua Tang

Masaru Honda

Robert L Sankman

Shrenik Kothari

Srinivas V Pietambaram

Brandon C Marin

Jeremy D Ecton

Dingying David Xu

Paul J Diglio

Mohit Mamodia

Takeshi Tamura

Arjun Krishnan

Kabirkumar Mirpuri

Kazutaka Noda

Aleksandar Aleksov

Feras Eid

Omkar G Karhade

Saikumar Jayaraman

Wei Ey Li

William J Lambert

Sairam Agraharam

Yonggang Li

Gang Duan

Edvin Cetegen

Hiroki Tanaka

Edward Rudolph Prack

Joe F Walczyk

Suddhasattwa Nad

Christopher L Rumer

Sergio Antonio Chan Arguedas

Nisha Ananthakrishnan

Vipul V Mehta

Masatoshi Deguchi

Kaizad Rumy Mistry

Naoto Yoshitaka

Bharat P Penmecha

Aastha Uppal

Masatoshi Shiraishi

Shan Zhong

Paul R Start

Mihir A Oka

Takashi Kumamoto

Akira Fukutomi

Shinji Okada

Haobo Chen

Yasuharu Iwashita

Ziyin Lin

Shengquan Ou

Liwei Wang

Hsin-Wei Wang

Yang Guo

Bohan Shan

Prasad Ramanathan

Xiaoxuan Sun

Jiro Harada

Hualiang Shi

Yasutaka Soma

Sufi Ahmed

Yawei Liang

Mark Allen

Jimmin Yao

Jigneshkumar P Patel

Soud Choudhury

Ifeanyi Okafor

Nai-Yuan Liu

Shweta Agrawal

Hao Wu

Huan Ma

Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

Hybrid bonding technologies with thermal expansion compensation structures

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Microelectronic assemblies including interconnects with different solder materials

An example microelectronic assembly comprises a support structure; an interposer above the support structure; a first die in the interposer, the first die including through-substrate vias (TSVs); and a second die in the interposer, the second die lacking TSVs. A die-to-package support (DTPS) interconnect field on a first face of the first die is substantially identical to a DTPS interconnect field on a first face of the second die, the DTP interconnect fields comprising a plurality of DTPS interconnects for connecting the first and second dies to the support structure. A die-to-die (DTD) interconnect field on a second face of the first die is substantially identical to a DTD interconnect field on a second face of the second die, the DTD interconnect fields comprising a plurality of DTD interconnects.

Low cost embedded integrated circuit dies

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

Microelectronic assemblies with direct attach to circuit boards

Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Semiconductor device stack-up with bulk substrate material to mitigate hot spots

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

Microelectronic component having molded regions with through-mold vias

An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.

Additively manufactured structures for heat dissipation from integrated circuit devices

Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

Thermally enhanced silicon back end layers for improved thermal performance

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

Barrier structures for underfill containment

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.

Wafer level passive heat spreader interposer to enable improved thermal solution for stacked dies in multi-chips package and warpage control

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

Backside metallization (BSM) on stacked die packages and external silicon at wafer level, singulated die level, or stacked dies level

Growing community of inventors

Chandler, AZ, United States of America

Xavier Francois Brun