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Xavier C Maitre

Jean-Pierre Petit

Alain M Thomas

Distributed arithmetic oversampling recursive digital filter comprising a recursive part constituted by q registers of a circulating nature, a non-recursive part of order p constituted by series registers, a memory divided into N memory blocks, a modulo N counter with .alpha. outputs, an adder--subtracter connected to the memory, an accumulator register, and a frequency clock f.sub.s. The filter is characterized in that the non-recursive part only comprises K series registers, K being an integer defined by the double inequality:

Distributed arithmetic oversampling recursive digital filter

Digital processing circuit forming a weighted sum of digital signals. It comprises n groups of M series registers (10/1, . . . , 10/nM) into which are introduced the signals to be processed, n multiplexers (15/1, 15/2, . . . , 15/n), a memory (20) containing precalculated quantities characteristic of the weighted sum to be formed, said memory having a capacity of 2 .sup..beta.+n words distributed into different blocks, a modulo M counter (25), an adder-subtracter (30) connected to the memory, an accumulator-register (40) connected to the adder-subtracter and a clock (50) actuating the counter and the registers. The circuit is in that the memory is subdivided into [M-(2.sup..beta. -M)] blocks of 2.sup.n words and into (2.sup..beta. -M) blocks of 2.sup.n+1 words, said blocks being selected by the bits supplied to the outputs of the counter, in that it comprises supplementary series registers, whose number is at the most equal to 2.sup..beta. -M, said series registers receiving the supplementary signals to be processed and in that it also comprises a multplexing means (21) controlled by the outputs of the counter.

Distributed arithmetic digital processing circuit

Transmission system of frequency division multiplex signals on a digital link. At the transmitting end of the digital line, the frequency division multiplex signals are sampled and coded into n-bit sample words. These sample words are transcoded into p-bit on-line words with p smaller than n through a transcoding procedure which makes a plurality k of successive levels of the n-bit code correspond to one and the same level of the p-bit code. The number k is selected depending on the maximal level reached by a sample word in a block of successive sample words. The number k is transmitted to the receiving end of the digital link by a control word for reverse transcoding of the on-line p-bit words into reconstituted n-bit sample words.

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Lannion, France

Xavier C Maitre