Bull Sas

Xavier Bru

Benoit Welterlen

Philippe Garrigues

Benoît Welterlen

Francois Wellenreiter

François Wellenreiter

A method designed to configure an IT system having at least one computing core for executing instruction threads, in which each computing core is capable of executing at least two instruction threads at a time in an interlaced manner, and an operating system, being executed on the IT system, capable of providing instruction threads to each computing core. The method includes a step of configuring the operating system being executed in a mode in which it provides each computing core with a maximum of one instruction thread at a time.

Method for configuring an it system, corresponding computer program and it system

The subject of the invention is in particular the optimization of standby management of a part of a microprocessor allowing implementation of at least two logic cores, said at least one microprocessor comprising means for placing at least one resource non common to said at least two logic cores on standby. After having determined () a desired standby state for each of said at least two logic cores, said desired standby state of one of said at least two logic cores is compared with the said desired standby state of the other of said at least two logic cores. In response to said comparison, instructions preparing for said placement on standby and/or allowing the restoration of said one of said at least two logic cores are launched ().

Method for optimizing management of standby of a microprocessor enabling the implementation of several logical cores and computer program implementing such a method

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Claix, France

Xavier Bru