Arm Limited

Xabier Iturbe

Balaji Venu

Emre Ozer

Emre Özer

Shidhartha Das

Antony John Penton

Milosch Meriac

Mbou Eyole

Reiley Jeyapaul

Matthew James Horsnell

David Michael Gilday

An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.

Memory scanning operation in response to common mode fault signal

Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.

Device, system and process for redundant processor error detection

A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

Reconfigurable circuit architecture

Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

Apparatus and method for increasing resilience to faults

Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

Methods and apparatus for anomaly response

An apparatuscomprises at least three processing circuitsto perform redundant processing of a common thread of program instructions. Error detection circuitryis provided comprising a number of comparatorsfor detecting a mismatch between signals on corresponding signal nodesin the processing circuits. When a comparatordetects a mismatch, this triggers a recovery process. The error detection circuitrygenerates an unresolvable error signalindicating that a detected area is unresolvable by the recovery process when, during the recovery process, a mismatch is detected by one of the proper subsetof the comparators. By considering fewer comparatorsduring the recovery process than during normal operation, the chances of unrecoverable errors being detected can be reduced, increasing system availability.

Error detection triggering a recovery process that determines whether the error is resolvable

An apparatus is provided comprising receiving circuitry to receive a representation of a circuit comprising a plurality of flops. Categorisation circuitry determines data dependencies between the flops from the representation and generates a categorisation of the flops into one of at least: a vulnerable category, a conditional category, and an isolated category, in dependence on the data dependencies. The categorisation indicates the vulnerability of the flops to transient errors. Output circuitry outputs the categorisation of the flops. The conditional category comprises those of the flops whose change in value is indicated by a change in a value in a corresponding flop in the flops or corresponding signal. The vulnerable category comprises those of the flops that are absent from the conditional category and whose change in value is affected by one of the flops or a signal and the isolated category comprises the flops that are absent from the conditional category and that are absent from the vulnerable category.

Vulnerability determination in circuits

An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.

Apparatus and method for checking output data during redundant execution of instructions

An apparatus and method are provided for increasing resilience to faults. The apparatus comprises processing circuitry for executing a plurality of code sequences including at least one critical code sequence, and configuration storage for storing mode control data for the processing circuitry. When the processing circuitry is executing a critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry, where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry. By increasing the resilience to faults, this reduces the chance that any such fault will manifest itself as an error in the processing operations being performed by the apparatus.

Disclosed are devices and methods for storing values, symbols, parameters or conditions in memory devices as states, and subsequently mapping detected states as values, symbols parameters or conditions. In one implementation write operations may place first and second memory elements in a particular impedance state selected from between a low impedance or conductive state and a high impedance or insulative state. The high impedance or insulative state represents a first binary value or symbol while the low high impedance or conductive state represents a second binary value or symbol. Subsequently detected impedance states of the first and second memory elements may be mapped to the second binary value or symbol responsive to either of the detected impedance states being the high impedance or insulative state and the second detected impedance state.

Method, system and device for error correction in reading memory devices

An apparatus comprises at least three processing circuits to perform redundant processing of common program instructions. Error detection circuitry coupled to a plurality of signal nodes of each of said at least three processing circuits comprises comparison circuitry to detect a mismatch between signals on corresponding signal nodes in said at least three processing circuits, the plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes. In response to the mismatch being detected in relation to corresponding signal nodes within the first group, the error detection circuitry is configured to generate a first trigger for a full recovery process for resolving an error detected for an erroneous processing circuit using state information derived from at least two other processing circuits. In response to the mismatch being detected in relation to corresponding signal nodes within the second group the error detection circuitry is configured to generate a second trigger for a targeted recovery process for a subset of components of the erroneous processing circuit. By implementing a targeted recovery process for a subset of components of an erroneous processing circuit a cheaper recovery process may be provided.

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Cambridge, United Kingdom

Xabier Iturbe