Analog Devices,inc.

Sicom, Inc.

Mediatek Corporation

Wyn T Palmer

Janos Kovacs

Kenny Gentile

Marc E Goldfarb

Steven R Robinson

Eric Martin Brombaugh

Jonathan Richard Strange

Edmund J Balboni

John M Liebetreu

Reuben Pascal Nelson

Kevin J McCall

Dan Zhu

Ziwei Zheng

Timir Raithatha

John Cavey

Fernando Viana

A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M).

Digital phase-locked loop clock system

A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks&#x2014;an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit.

Exact frequency translation using dual cascaded sigma-delta modulator controlled phase lock loops

A clock frequency divider for odd numbered divide ratios. The divider clocks two counters in parallel from a reference clock to be divided. One counter is loaded with the divide ratio and the other counter is loaded with the divide ratio except for the least significant bit. The second counter will set a latch when its count has elapsed. The first counter will reset the latch when its count has elapsed and will reload the counters. The latch is used for the divided output, but passes through a retiming circuit. The retiming circuit delays the output edge by one reference clock edge when the least significant bit indicates an odd numbered divide ratio.

Symmetry corrected high frequency digital divider

A multi-branch frequency translation system converts a plurality of independent input clocks to a common frequency. One of the converted clock signals is selected as a dominant clock. The remaining converted clock signals are edge-synchronized with the dominant clock. When the system selects another converted clock signal for use as the dominant clock, the newly selected signal already is edge-synchronized with the dominant clock and, therefore, switchover losses can be avoided. The dominant clock can be subject of further frequency translation processes and output from the system.

Multiple input PLL with hitless switchover between non-integer related input frequencies

A phase-locked loop frequency synthesizer has a charge pump, phase-locked loop filter, voltage-controlled oscillator, and a bandwidth calibration circuit. The bandwidth calibration circuit measures the gain of the voltage-controlled oscillator and uses the measured voltage-controlled oscillator gain to adjust the charge pump level. The charge pump level is adjusted so that a product of the voltage-controlled oscillator gain and the measured charge pump level results in a constant phase-locked loop bandwidth.

Phase-locked loop bandwidth calibration circuit and method thereof

A direct conversion receiver having a homodyning section fed by a received radio frequency signal having a carrier frequency and reference signal having the carrier frequency; and a filter coupled to the monodyning section. The filter includes a plurality of serially coupled high pass filter stages. The high pass filter section acts as a DC offset correction loop that eliminates the serial effect of many amplifier sections on DC offsets arising within components, while maintaining a sufficiently low cutoff frequency to avoid adversely impacting information integrity at higher frequencies. The high pass filter sections also enable the integration of the needed capacitors, thus minimizing external components and connections. Each filter stage includes an amplifier and a low pass filter coupled in a negative feedback arrangement with the amplifier. Each low pass filter is adapted to have the cutoff frequency thereof switch from an initial high cutoff frequency to a subsequent lower cutoff frequency. A high filter stage of a direct conversion receiver is provided that includes in a low pass filter feedback section thereof a capacitor and a resistor section coupled to the capacitor. The section includes a switch for changing the resistance of the resistance section. The resistance has a first resistance value during an initial phase and a second resistance value during a subsequent phase. A switching arrangement charges the capacitor rapidly during an initial, start-up time period or after a large step change in the gain of the amplifier.

Direct conversion receivers and filters adapted for use therein

A filter having a semiconductor chip and a low pass filter section on the chip. The low pass filter section includes a filter transconductor and a filter capacitor connected to the filter capacitor. The low pass filter section has a cut-off frequency related to the transconductance, gm,, of the filter transconductor and the capacitance of the filter capacitor. A gm control circuit having a control circuit transconductor is provided. The gm control circuit includes a first oscillator for producing a reference frequency. The first oscillator has a portion thereof on the chip and an off-chip capacitor and off-chip resistor. The reference frequency is a function of the capacitance of the off-chip capacitor and the resistance of the off-chip resistor. A second oscillator is on the chip and produces a variable frequency. The second oscillator has an on-chip capacitor. The variable frequency is a function of the capacitance of the on-chip capacitor and on-chip transconductor, gm,, such variable frequency is controlled by a control circuit transconductor control signal. A control loop is provided. The control loop is responsive to a difference between the reference frequency and the variable frequency and such loop produces the a feedback signal to drive the variable frequency towards the reference frequency.

Filter having minimized cut-off frequency variations

A digital data receiver includes a tunable analog matched filter circuit having a variable bandwidth responsive to the bit error rate (BER) of the decoded data. The bandwidth of the analog filtering circuit is controlled by a tuning control signal that includes a coarse tuning signal combined with a fine tuning signal. The coarse tuning signal is generated by a frequency-to-current converter and the fine tuning signal is generated by a current-scaling digital-to-analog converter (DAC). The DAC input signal is produced by a DAC control circuit that includes a BER comparator and a DAC control state machine. The BER comparator determines whether the BER has improved or degraded in response to a previous tuning command. To optimize the BER in the decoded data signal, the state machine increments or decrements the value of the fine tuning signal, which in turn alters the filter bandwidth.

Digital receiver with tunable analog filter and method therefor

A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

All-MOS precision differential delay line with delay a programmable

A charge pump system for charging an integrating capacitor includes a current source for supplying a first current of a first polarity, a second current of the opposite polarity which is a fraction of the first current, a third current of the opposite polarity, and a fourth current of the first polarity which is a fraction of the third current, and a switching device for simultaneously interconnecting both the first and second currents to the integrating capacitor to provide a first pump down charging current which is the fractional difference between the first and second currents, and also alternately selectively interconnecting both the third and fourth currents to the integrating capacitor to provide a second pump up charging current which is a fractional difference between the third and fourth currents and opposite in polarity to the first charging current.

Charge pump system

An intrinsic R2R resistance ladder digital to analog converter (DAC) includes a plurality of matched semiconductor ladder switches, one in each of the R and 2R legs of the R2R ladder. The ON resistance of each semiconductor switch being matched to constitute the resistance ladder of the DAC; the ladder switches being operated in response to the digital signal input to the DAC; a reference circuit including a reference semiconductor switch matched with the ladder switches responsive to a reference current to generate a reference voltage; and a voltage follower circuit for monitoring the reference voltage and adjusting the current through the ladder switches to match the voltage at each ladder switch with the reference voltage for precisely fixing the DAC analog output current as a proportion of the reference current in dependence upon the operation of the ladder switches by the digital input signal.

Intrinsic R2R resistance ladder digital to analog converter

A hybrid analog/digital automatic gain control gain recovery system includes a variable gain amplifier (VGA) for receiving a variable amplitude input signal; a first AGC loop includes an analog to digital converter (DAC) for receiving the analog input signal and converting it to a digital signal; a digital gain error detection circuit for detecting variations of the digital signal in a first range and generating a digital error correction signal; and a digital to analog converter (DAC) for converting the digital error correction signal to a first analog correction signal; a second analog AGC loop includes an analog gain error detection circuit, responsive to variations in the output of the VGA in a second range greater than the first range for generating a second analog correction signal; and an integrator circuit responsive to the first and second analog correction signals for providing to the VGA a control signal to adjust the gain of the VGA to accommodate variations in the input signal amplitude.

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Reading, MA, United States of America

Wyn T Palmer