Cadence Design Systems, Inc.

Lucent Technologies Inc.

Wuudiann Ke

Kumar Venkatramani

Henry C Chang

Grant Edmund Martin

Christopher K Lennard

Merrill Hunt

Larry Cooke

Khoan Truong

Peter Paterson

Duy K Le

A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Blocked based design methodology

Block based design methodology

In accordance with the present invention, an apparatus and method for implementing a new user-defined B-S instruction called PINCONTROL is disclosed. When PINCONTROL is in effect, an output pin can be configured to be either driving a constant 0, driving a 1, in the high-impedance (high-Z) state or in the control of system logic; and different pins of the same chips may assume different configurations depending on the content of the capture and update portion of the B-S register. This instruction provides an improved fault insertion capability. For example, if it is desired to inject a stuck-at-0 fault at pin p, pin p can be configured to drive a constant 0 while allowing other pins to function normally. A stuck-at-1 fault can also be injected by configuring pin p to drive a constant 0 while allowing other pins to function normally. An open fault can also be injected by configuring pin p into a high-impedance state. As will described, multiple faults of the same or different type may be injected, as can transient faults with different durations. This kind of fault insertion capability can be used to verify the fault-tolerant capability of a fault-tolerant system and for the verification of system diagnostics software.

Apparatus and method for hybrid pin control of boundary scan applications

A backplane testing method is provided in which test vectors are applied to individual circuit boards in a system while remaining circuit boards in the system are disabled. The signals on all receivers in the system are observed during testing. The circuit boards are connected to a test bus in a multi-drop arrangement, so that individual circuit boards can be addressed using slave interfaces. A walking enable technique is used to systematically toggle all of the drivers on the circuit boards. An intraboard testing technique is used for applying test vectors including an all 0's vector, an all 1's vector, and a series of test vectors generated from a binary counting sequence. Backplane faults are identified by comparing the observed receiver signals to the signals expected in response to the applied test vectors.

Methods for backplane interconnect testing

Pseudorandom Boundary-Scan testing of a interconnects within a system (10) is accomplished by first generating a pseudorandom pattern and then filtering the pattern before application to the system to modify values within each pattern that could cause a signal conflict. Each response generated by the system upon application to the system is also filtered to mask non-deterministic values with the response. The filtered response is compared to a set of signatures representing a fault-free condition to detect faults within the system.

Method and apparatus for pseudorandom boundary-scan testing

Verification of test information transmitted across an 1149.1 backplane test bus between a circuit board (12.sub.1) and a test master (14) is accomplished by having both the test master and the circuit board compute a cheek code for each block of information that is transmitted by, or received at, the board. During intervals other than one of the active Boundary-Scan states, the test master (14) acquires the check codes produced at the circuit board (12.sub.1) and compares them to the corresponding codes generated by the tests master. Any difference between the corresponding codes generated by the test master and the circuit board signifies a transmission error.

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Cupertino, CA, United States of America

Wuudiann Ke