Altera Corporation

Wuu-Cherng Lin

Andy Louie Lee

Thomas Henry White

Giles V Powell

Bradley Jensen

Dustin Do

Swee Aun Lau

Fangyun Richter

Che Ta Hsu

Wen Sun Wu

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

N-well/P-well strap structures

Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.

Methods of forming gate structures for reduced leakage

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San Jose, CA, United States of America

Wuu-Cherng Lin