Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

International Business Machines Corporation

Infineon Technologies Ag

Infineon Technologies North America Corp.

Wuping Liu

Bei Chao Zhang

Juan Boon Tan

Liang Choo Hsia

Fan Zhang

Yeow Kheng Lim

Tae Jong Lee

Alan Cuthbertson

Beichao Zhang

John Anthony Fitzsimmons

Liang-Choo Hsia

Michael Beck

Chin Chuan Neo

Wei Liu

Huang Liu

John Leonard Sudijono

Hermann Wendt

Wei Lu

Johnny Widodo

Dong Kyun Sohn

Larry Clevenger

Teck Jung Tang

Wei Shao

Raymond Joy

Kho Liep Chok

Jing Li

Xian Bin Wang

Boon Meng Seah

Vish Srinivasan

Luying Du

Han Wah Ng

Shyam Pal

Jing Hui Li

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto. A contact opening exposing the metal silicide is formed to the semiconductor device. A conductive material is deposite within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact. A self-aligned conductive material is deposited within the contact to form a conductive plug that at least partially fills the contact seam void, and a metallization layer is deposited overlying the contact.

Methods for fabricating integrated circuits having device contacts

A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

Integrated circuit system employing low-k dielectrics and method of manufacture thereof

An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.

Integrated circuit hard mask processing system

An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.

Method of controlled low-k via etch for Cu interconnections

An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.

Structure and method to prevent charge damage from e-beam curing process

An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Integrated circuit manufacturing method using hard mask

An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects

An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.

Method to fabricate aligned dual damascene openings

A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.

Metal barrier cap fabrication by polymer lift-off

In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an 'oxide ring'. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The 'oxide ring' of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.

Method of fabrication of a die oxide ring

In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.

Self-patterning of photo-active dielectric materials for interconnect isolation

An integrated circuit manufacturing method includes providing a base, forming a first conductor, forming a first barrier layer, forming a first dielectric layer, and forming a masking layer. The method further including forming a first via opening in the masking layer, forming a first trench opening in the masking layer, and simultaneously forming a second via opening in a layer under the masking layer, and forming a second trench opening through the masking layer and in the layer under the masking layer and simultaneously forming a third via opening in another layer under the masking layer. The method further including removing the first barrier layer using the third via opening and the masking layer to form a trench and a via, and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.

Integrated circuit with simultaneous fabrication of dual damascene via and trench

A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. Simultaneously patterning the patterned middle dielectric material layer using the patterned upper dielectric layer as a mask to form an inchoate upper trench opening; and the lower dielectric material layer using the patterned mask layer and the patterned middle etch stop layer as masks to form an inchoate lower via opening aligned with the inchoate upper trench opening.

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Singapore, Singapore

Wuping Liu