Skhynix Inc.

Hynix Semiconductor Inc.

Wun Mo Yang

Gun Woo Yeon

Ki Sung Kim

Jeong Soon Kwak

Dong Kyu Lee

Kyeong Rho Kim

Myung Suk Lee

Yi Chun Liu

A Peripheral Component Interconnect express (PCIe) device includes a Direct Memory Access (DMA) device including a plurality of functions; and a PCIe interface device for performing communication between a host and the DMA device. The PCIe interface device includes a reset operation controller for, when a plurality of reset signals are received from the host, grouping operations, which are the same as one another among reset operations respectively corresponding to the plurality of reset signals, determining a processing order of the reset operations, and performing the reset operations according to the processing order.

Peripheral component interconnect express device and operating method thereof

Provided herein may be a storage device including a memory device, and a memory controller including a plurality of cores. The memory controller may load a boot loader image for firmware update running in a memory of a core arbitrarily selected from among the plurality of cores, receive a new firmware image from a host in response to the boot loader image that is executed in the selected core, and update a firmware image stored in a memory of each of the plurality of cores with the new firmware image.

Storage device and method of operating the same

Various embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the nonvolatile memory apparatus may include: a host interface; a memory controller coupled to the host interface; and a memory area including a plurality of chips controlled by the memory controller. The memory controller may be configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on the total erase count (TEC) of each logical group, and perform wear-leveling in stages.

Nonvolatile memory apparatus for performing wear-leveling and method for controlling the same

A solid state storage system includes a flash memory area and a memory controller. The flash memory area includes memory blocks and replacement blocks configured to replace bad blocks occurring within the memory blocks. The memory controller is configured to perform a logical-to-physical address mapping on logical blocks including the replacement blocks, and select the replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks.

Solid state storage system for controlling reserved area flexibly and method for controlling the same

A semiconductor storage system includes a memory controller that classifies a memory block of a memory area into a data block and a buffer block. The buffer block corresponds to the data block. The memory controller compares the number of free pages of both the data block and the buffer block with the number of valid pages of the data block and the buffer block during mergence in order to select the merged target block. Depending on the result of the comparison, either the data block or the buffer block is selected as the merged target block.

Growing community of inventors

Ichon-si, South Korea

Wun Mo Yang