Qualcomm Incorporated

Wu-Hsin Chen

Li Liu

Chirag Dipak Patel

Aleksandar Miodrag Tasic

Vinod Panikkath

Timothy Donald Gathman

Klaas Van Zalinge

Sasha Vujcic

Yunfei Feng

Shrenik Patel

Chuan Wang

Masoud Moslehi Bajestan

Gurkanwal Singh Sahota

Abdellatif Bellaouar

Chiewcharn Narathong

Frederic Bossu

Steven C Ciccarelli

Prasad Srinivasa Siva Gudem

Ojas Choksi

Haitao Cheng

Yi Zeng

Kang Yang

Hong Sun Kim

Muhammad Hassan

Sher Jiun Fang

Rui Xu

Zixiang Yang

Marco Vigilante

Jianyun Hu

Sriramgopal Sridhara

Yanming Xiao

Arpit Gupta

Kiyong Choi

Xiaotie Wu

A radio system architecture includes a receiver having multiple sub arrays in a phased array, the multiple sub arrays configured to perform carrier aggregation (CA) and multiple input multiple output (MIMO) signal processing, and provide independent beam management for multiple radio frequency (RF) signals received at each of the multiple sub arrays, and a data processor configured to receive signals from the receiver and extract information regarding wireless communications.

Phased array antenna architecture

Aspects of the disclosure relate to wireless communication apparatuses, methods, and other aspects of sliding intermediate frequency filters for carrier aggregation communications. One aspect a high band mixer including a radio frequency (RF) receive signal input, a local oscillator (LO) input, and an IF signal output, a tunable high pass filter including an input and an output, an intermediate frequency (IF) received signal multiplexer including a merged IF CA signal output, a first input, and a second input, an LO input, and an IF signal output, where the RF receive signal input is coupled to the low band mmW CA receive port, and a tunable low pass filter including an input and an output, where the input is coupled to the IF signal output of the low band mixer, and where the output is coupled to the second input of the IF received signal multiplexer.

Intermediate frequency filter for millimeter-wave carrier aggregation

In certain aspects, a system includes a voltage-controlled oscillator (VCO), a phase detector configured to receive a reference signal, a frequency divider coupled between an output of the VCO and the phase detector, a phase-to-current circuit coupled to an output of the phase detector, and a temperature circuit configured to output a temperature-dependent voltage. The system also includes a switching circuit configured to selectively couple the phase-to-current circuit to an input of the VCO and configured to selectively couple the temperature circuit to the input of the VCO.

Dual-path phase locked loop (PLL) with closed-loop VCO temperature compensation

Aspects described herein include devices and methods with chain routing of signals for massive antenna arrays. In some aspects, an apparatus is provided that includes a first millimeter wave (mmW) transceiver having a first port, a second port, one or more antenna elements, a plurality of chain mmW transceiver ports, and switching circuitry. The switching circuitry is controllable by control data to route portions of a merged clock and data signal and a merged control and data signal between a first route between the one or more antenna elements and the first port and a second route between the one or more antenna elements and the second port and a third route between the first port and the plurality of chain mmW transceiver ports and a fourth route between the second port and the plurality of chain mmW transceiver ports.

Split chaining for large phase array systems

In certain aspects, an apparatus includes a transformer including an input inductor and an output inductor, wherein the input inductor is magnetically coupled to the output inductor. The apparatus also includes a transconductance driver configured to drive the input inductor based on an input signal. The apparatus further includes a feedback circuit configured to detect an output voltage swing at the output inductor, generate a regulated voltage at the input inductor, and control the regulated voltage based on the detected output voltage swing.

Swing tracking and control

A low-pass filter having a notch frequency due to a resonance between a mutual inductance of inductive elements and a capacitance. An exemplary low-pass filter generally includes a first inductive element having a first terminal and a second terminal, the first terminal being coupled to the input port, and a second inductive element having a first terminal and a second terminal, the first terminal of the second inductive element being coupled to the second terminal of the first inductive element and the second terminal of the second inductive element being coupled to the output port. The filter also includes a shunt capacitive element coupled to the second terminal of the first inductive element, wherein a mutual inductance between the first inductive element and the second inductive element and a capacitance of the shunt capacitive element are configured to have a resonance providing a notch frequency for the low-pass filter.

Low-pass filter utilizing mutual inductance

A multi-stage low-noise amplifier (LNA) device with a band pass response includes a first LNA in series with a second LNA. The device further includes multiple outputs coupled to the second LNA. Each of the outputs is capable of being active at the same time. The device further includes a high pass filter coupled between the first LNA and the second LNA.

Multi-stage bandpass low-noise amplifier

A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node.

Systems and methods providing an intermodulation distortion sink

A reconfigurable filter circuit has a first path including a transimpedance amplifier (TIA). The transimpedance amplifier has an input that receives an input current and an output that outputs a voltage. The reconfigurable filter circuit also includes a switchable feedback path. The switchable feedback path includes a first low-pass filter coupled to an output of the TIA. The switchable feedback path also includes a first switch to couple the feedback path to provide a feedback current to the first path resulting in a bandpass response in the output voltage when the switch is closed and a low-pass response in the output voltage when the switch is open.

Reconfigurable radio frequency (RF) bandstop/intermediate frequency (IF) bandpass filter

A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.

Configurable mixer

A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.

Frequency divider with duty cycle adjustment within feedback loop

In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel pull-up circuit pulls up on a second output node QB of the latch. A second P-channel pull-up circuit pulls up on a first output node Q of the latch. A pull-down circuit involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.

Pseudo-CML latch and divider having reduced charge sharing between output nodes

A method for reducing power consumption on a wireless communication device is described. The wireless communication device includes a first stage active filter and a second stage active filter. A condition measurement is obtained that includes a signal measurement condition. If it is determined that the condition measurement is above a threshold, the second stage active filter is bypassed.

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San Diego, CA, United States of America

Wu-Hsin Chen