Nan Ya Technology Corporation

Wu-Der Yang

Chun-Huang Yu

Tean-Sen Jen

Ching-Feng Chen

Shiou-Yu Wang

Jui-Chung Hsu

Chia-Chi Hsu

Chang-Pin Chen

Chang-Chun Hsieh

A memory device and a method for protecting the same are provided. The memory device includes: a random number generator, a counter, and a controller. The random number generator includes a first logic gate and a second logic gate configured to generate a first output and a second output, respectively, according to the address of the first word line and the address of the first accessed word line. The random number generator further includes a switch configured to select one of the first output and the second output to be a first number. The counter is configured to receive the first number and count down from the first number. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh adjacent word lines of the second accessed word line during a second refresh cycle.

Memory devices including mechanism of protecting a vulnerable word line based on the previous refreshed word lines and relevant methods

A semiconductor package includes a first substrate, a first semiconductor chip, a first bonding wire, a second substrate, a second semiconductor chip and a second bonding wire. The first substrate has a window through a center portion of the first substrate. The first semiconductor chip is located on the first substrate. The first bonding wire is in the window of the first substrate and electrically connects to the first semiconductor chip and the first substrate. The second substrate is located on the first semiconductor chip, and has a window through a center portion of the second substrate. The second substrate electrically connects to the first substrate. The second semiconductor chip is located on the second substrate. The second bonding wire is in the window of the second substrate and electrically connects to the second semiconductor chip and the second substrate.

Semiconductor package and manufacturing method thereof

A method for adaptive noise suppression on data strobe signals is provided. The method includes the following steps: determining whether a first data strobe signal and a second data strobe signal satisfy a first condition; in response to the first data strobe signal and the second data strobe signal satisfying the first condition, determining whether a mode register setting value (MRSV) associated with a first on-die terminator and a second on-die terminator is greater than N; and in response to the MRSV being not greater than N, decoupling a first resistor and a second resistor from a first input terminal and a second input terminal of a differential amplifier, respectively; and in response to the MRSV being greater than N, coupling the first resistor and the second resistor to the first input terminal and the second input terminal of the differential amplifier, respectively.

Method for adaptive noise suppression on data strobe signals and memory device using the same

A method for controlling data strobe signals for use in a memory device is provided. The memory device includes a receiver circuit having a differential amplifier, an auxiliary control circuit, and a data strobe control circuit. The method includes the following steps: utilizing the differential amplifier to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal; utilizing the auxiliary control circuit to generate a disable control signal using the first data strobe signal and the second data strobe signal; and disabling the data strobe control circuit in response to the disable control signal being in a high logic state.

Memory device with receiver circuit to suppress noise on data strobe signals

A memory system includes a controller and a memory circuit. Controller outputs a first data strobe signal and a second data strobe signal. Memory circuit is coupled to controller, and is configured to receive first data strobe signal and second data strobe signal. Memory circuit includes a receiver. Receiver includes a logic conversion circuit. Logic conversion circuit is coupled to controller. When first and second data strobe signal are at the same voltage level, logic conversion circuit is configured to convert first second data strobe signals into third and fourth data strobe signals. Third data strobe signal and fourth data strobe signal converted by logic conversion circuit are at different voltage levels. When first and second data strobe signals are at different voltage levels, logic conversion circuit is configured to pass first and second data strobe signal and as third and fourth data strobe signals.

Memory system and receiver

A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh one of a plurality of word lines during a first refresh cycle in response to a refresh signal, a random number generator configured to generate a first number, a counter configured to receive the first number as an initial value of the counter, wherein the counter is configured to be turned on in response to the refresh signal, and an address register configured to store an address of a first word line active when the counter decrements to zero. The controller is configured to obtain the address of the first word line and protect a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line.

Memory devices having protection circuit for protecting word line

A package structure includes a first substrate, a second substrate, a chip, a first wire and a second wire. The first substrate includes a top surface, a bottom surface, a window and a first conductive pad. The bottom surface of the first substrate is opposite to the top surface. The window communicates the top surface and the bottom surface. The first conductive pad is located over the bottom surface. The second substrate is located over the first substrate. The second substrate is spaced from the first substrate and includes a second conductive pad facing the top surface of the first substrate and exposed from the window. The chip is located over the second substrate. The first wire connects the first conductive pad to the second conductive pad. The second wire connects the second conductive pad to the third conductive pad.

Package structure and method of forming thereof

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a decoupling capacitor structure, and an electronic component. The decoupling capacitor structure is disposed on the substrate. The electronic component is disposed on the decoupling capacitor structure and electrically connected to the decoupling capacitor structure. The electronic component is stacked over the decoupling capacitor structure.

Semiconductor device with decoupling capacitor structure and method for manufacturing the same

A memory device is provided, which includes a memory cell array, a control circuit, and an interface circuit. The interface circuit includes a receiver circuit configured to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state the second data strobe signal satisfying a predetermined condition, the receiver circuit adjusts a third logic state of the third data strobe signal and/or a fourth logic state of the fourth data strobe signal. The control circuit performs a write operation on the memory cell array according to the write command, the third data strobe signal, and the fourth data strobe signal.

Memory device and method for adjusting logic states of data strobe signals used by memory device

A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh a first word line and a first protected word line during a first refresh cycle in response to a refresh signal, a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number, a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to be turned on in response to the refresh signal. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh a second protected word line, adjacent to the second accessed word line, during a second refresh cycle.

Memory devices selecting and protecting a possible attacked word line based on the previous refreshed word lines and the relevant methods

A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh one of word lines during a first refresh cycle in response to a refresh signal, a number trimmer configured to generate a modified first number according to a first number generated by a random number generator, wherein the modified first number is less than a first predetermined number. The memory device further includes a counter configured to receive the modified first number as an initial value, and to be turned on in response to the refresh signal. The controller is configured to obtain an address of a first word line being accessed when the counter counts to zero, and refresh a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line.

Memory devices having a random number generator for protecting memory cells, and methods for protecting memory devices

A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure extending along a first direction and electrically connected to a first transistor, a second gate structure extending along the first direction and electrically connected to a second transistor, a first active region extending along a second direction different from the first direction and across the first gate structure and the second gate structure, and a first conductive element extending along the second direction and disposed on the first active region. The first conductive element is electrically connected to the first active region. The first conductive element is electrically connected to the first active region, such that a short circuit between the first active region and the third transistor is formed. The first gate structure and the first active region form a first fuse element, and the second gate structure and the first active region form a second fuse element.

Semiconductor device structure

A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a carrier having a first surface and a second surface opposite to the first surface of the carrier. The carrier has a through hole filled with a first package body and extending between the first surface and the second surface of the carrier. The WBGA package also includes an electronic component disposed on the second surface of the carrier. The electronic component includes a first bonding pad and a second bonding pad. The WBGA package also includes a first bonding wire electrically connected between the first bonding pad and the second bonding pad.

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Taoyuan, Taiwan

Wu-Der Yang