Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Seagate Technology Incorporated

Wu Chang

Shaohua Yang

Fan Zhang

Ming Jin

Haitao Xia

Zongwang Li

Yang Han

Razmik Karabed

Victor A Krachkovsky

Xuebin Wu

Weijun Tan

Chung-Li Wang

Changyou Xu

Jun Xiao

Parviz Rahgozar

Yoon Liong Liow

Erich Franz Haratsch

Lei Chen

Kelly K Fitzpatrick

Jianzhong Huang

Madhusudan Kalluri

Han Fang

Adbel Hakim S Alhussien

Systems and methods relating generally to data storage, and more particularly to systems and methods for encoding to modify the size of an information set.

Systems and methods for high throughput multi-input compression

A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases, and a decoder operable to decode the data set after it is read from the storage medium.

Multi-level enumerative encoder and decoder

Various systems and methods for media defect detection.

Systems and methods for short media defect detection using multi-iteration soft data feedback

Variations of the Nelder-Mead direct search method are employed to find read channel parameter settings in a discrete field having three or more dimensions. The three or more dimensions correspond to read channel parameters, at least some of which are highly correlated. The steps of the Nelder-Mead method are executed according to a methodology to arrive at substantially optimal parameter settings for a read channel, even where a discrete function defining parameter outcomes is noisy. In some embodiments, dimensional collapse, considered inefficient in a two-dimensional field, is allowed in order to reach an optimal solution in a greater-than-two-dimensional field.

Multi-dimensional optimization of read channel

Systems and methods for data processing particularly related local iteration randomization in a data decoding circuit. In some cases a data processing system may include: a layered data decoding circuit, a value generator circuit, and a selector circuit. The layered data decoding circuit is configured to iteratively apply a data decoding algorithm up to a selected number of times to a decoder input to yield a decoded output in accordance with a layer order. The value generator circuit is operable configured to generate an adjusted number of times where the adjusted number of times is less than a default number of times. The selector circuit is operable configured to select one of the default number of times and the adjusted number of times as the selected number of times.

Systems and methods for enhanced local iteration randomization in a data decoder

Methods and apparatus are provided for detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and decoding the plurality of bits using a binary decoder. The non-binary log likelihood ratio captures one or more of intra-page correlations and/or intra-cell correlations. A least significant bit and a most significant bit of a given cell can be independently converted and/or jointly converted to the non-binary log likelihood ratio.

Detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window

The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.

Method and system for generation of a tie-breaking metric in a low-density parity check data encoding system

Systems and methods for computing sign disagreement between signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector; and detecting one or more consecutive sign disagreements between an extrinsic output of a detector and an extrinsic output of a decoder.

Pattern-dependent short media defect detection

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit.

Systems and methods for anti-causal noise predictive filtering in a data channel

Various embodiments of the present invention provide systems and methods for format efficient data storage. As an example, a data storage device is described that includes: a storage medium, a read/write head assembly, and a read channel circuit. The read/write head assembly is disposed in relation to the storage medium and operable to sense information corresponding to an encoded codeword. The read channel circuit is operable to receive the encoded codeword. The read channel circuit includes a missing symbols insertion circuit, a codeword de-scramble circuit, an address insertion circuit, and a data decoder circuit. The missing symbols insertion circuit, the codeword de-scramble circuit, and the address insertion circuit together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword. The data decoder circuit is operable to apply a data decoding algorithm to the modified encoded codeword to yield a decoded output.

Systems and methods for data addressing in a storage device

A method of generating a hardware encoder includes generating a first directed graph characterizing a constraint set for a constrained system, identifying a scaling factor for an approximate eigenvector for the first directed graph, applying the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector, partitioning arcs between each pair of states in the first directed graph, performing a state splitting operation on the first directed graph according to the partitioning of the arcs to yield a second directed graph, and generating the hardware encoder based on the second directed graph.

Encoder and decoder generation by state-splitting of directed graph

An apparatus includes a low density parity check decoder operable to iteratively generate messages between a plurality of check nodes and variable nodes, and to calculate a fractional quality metric for a data block as it is decoded in the low density parity check decoder based at least in part on perceived values of data in the variable nodes. The fractional unsatisfied check quality metric is a probabilistic determination of a number of unsatisfied parity checks in the low density parity check decoder.

LDPC decoder with fractional unsatisfied check quality metric

Systems, methods, devices, circuits for data processing, and more particularly to data processing including adjacent track interference mitigation.

Systems and methods for ATI mitigation

Systems and method relating generally to data processing, and more particularly to systems and methods for determining head stability.

Systems and methods for slider head stability determination

The present invention is related to systems and methods for enhancing data detection in a data processing system. In one embodiment, a data processing system is disclosed that includes a data detector circuit that is governed at least in part based upon selected coefficients. The selected coefficients are selected as either a first set of coefficients or a second set of coefficients where the second set of coefficients has fewer coefficients than the first set of coefficients.

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Santa Clara, CA, United States of America

Wu Chang