Samsung Electronics Co., Ltd.

Woun-Suck Yang

Se-Myeong Jang

Jae-Man Yoon

Min-sang Kim

Hyun-Ju Sung

Dong-Gun Park

Makoto Yoshida

Chul Ho Lee

Keun-Nam Kim

A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

Recessed transistor and method of manufacturing the same

A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars. A source/drain region is formed in a region of the active expanding region adjacent to the gate, thereby resulting in a multi-channel transistor structure.

Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method

In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.

Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer

Semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer and method of fabricating the same

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Suwon-si, South Korea

Woun-Suck Yang