Lg Display Co., Ltd.

WooSung Shim

SangHun Yoon

JunHo Bong

A gate driver and a display device including the same, are discussed. The gate driver includes a plurality of stages which are dependently connected to each other. Each of the plurality of pixels includes an output unit which outputs a gate voltage by a voltage of an RQ node, a voltage of a PQ node, and a voltage of a QB node, a first controller which controls the RQ node, a second controller which controls the PQ node, and a third controller which controls the QB node. The gate voltage is configured by a first clock signal having a first phase and a second clock signal having a first phase which is different from the first phase of the first clock signal.

Gate driver that outputs gate voltage based on different signals and display device including the same

A gate driver and a display device including the same, are discussed. The gate driver includes a plurality of stages which are dependently connected to each other. Each of the plurality of pixels includes an output unit which outputs a gate voltage by a voltage of an RQ node, a voltage of a PQ node, and a voltage of a QB node, a first controller which controls the RQ node, a second controller which controls the PQ node, and a third controller which controls the QB node. The gate voltage is configured by a first clock signal having a first phase and a second clock signal having a second phase which is different from the first phase.

Gate driver for improving luminance and display device including the same

Disclosed herein is a gate driver including a plurality of stages. The nth stage of the plurality of stages includes a first scan signal output unit configured to output the kth clock as a first scan signal through a first scan signal output node when a voltage of a Q-node is at a high state, and an emission control signal output unit configured to output a gate high voltage through an emission control signal output node when a voltage of the first scan signal output node and a voltage of an EQ-node are at the high state by an emission control clock. The emission control signal output unit is electrically connected to the Q-node. The gate driver includes a scan signal output and an emission control signal output, so that GIPs having the same configuration can be disposed on the left and right sides of a display panel.

Simplified gate driver configuration and display device including the same

The gate driving circuit includes a shift register including a plurality of stages. An n-th stage among the plurality of stages includes: a pull-up switching element outputting a first clock to an output node in accordance with a voltage in a Q node, a pull-down switching element outputting a gate low voltage VGL to the output node in accordance with a voltage in a QB node, and a logic unit inverting and outputting a voltage in the Q node and a voltage in the QB node. The logic unit includes a first switching element including a gate to which a fourth clock is input and being between a start voltage line which supplies a start voltage and the Q node, a second switching element including a gate connected to the Q node and being connected to the QB node, a third switching element being between the second switching element and a gate low voltage line which supplies the gate low voltage, a fourth switching element including a gate to which a third clock is input and being between a gate high voltage line which supplies a gate high voltage and the QB node, a fifth switching element including a gate connected to the QB node and being between the Q node and the gate low voltage line, a first capacitor between the Q node and the output node, and a second capacitor between the gate low voltage line and the gate of the pull-down switching element.

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Hwaseong-si, South Korea

WooSung Shim